代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/281861/9128730
vhd and8.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and8 IS
PORT(
a1,a2,a3,a4,a5,a6,a7,a8 : IN STD_LOGIC;
y : OUT STD_LOGIC);
END and8;
ARCHITECTURE behavier OF and8 IS
BEGIN
y
www.eeworm.com/read/281861/9128776
vhd freqdetect_top.vhd
Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY freqdetect_top IS
PORT(clk : IN STD_LOGIC; --clk时钟
sign : IN STD_LOGIC; --待测信
www.eeworm.com/read/183819/9136569
cmp ddr_sdram.cmp
-- Generated by DDR SDRAM Controller 3.2.0 [Altera, IP Toolbench v1.2.9 build43]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS
www.eeworm.com/read/183580/9153001
vhd pkg_prims.vhd
--
-- Risc5x
-- www.OpenCores.Org - November 2001
--
--
-- This library is free software; you can distribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as pu
www.eeworm.com/read/183529/9155599
vhd rs232_send.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rs232_send is
port (clk,load,reset:in std_logic;
datain: in std_logic_vector(7 downto 0);
www.eeworm.com/read/183154/9177161
txt jiafaqimiaoshu.txt
加法器描述
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
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vhd min4_e.vhd
----------------------------------------------------------------------
---- ----
---- min4_e.vhd
www.eeworm.com/read/182737/9193597
vhd trellis1_e.vhd
----------------------------------------------------------------------
---- ----
---- trellis1_e.vhd
www.eeworm.com/read/182277/9209349
vhd multi8x8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ANDARITH IS --选通与门模块
PORT (ABIN:IN STD_LOGIC; --与门开关
DIN:IN STD_LOGIC_VECTOR (7 DOWNTO 0); --8位输入
D
www.eeworm.com/read/182027/9221887
txt ps2_vhdl.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ps2 is
port
(
kd:in std_logic;
clkin : in std_logic;
kc:in std_logic;
led:out std_logic_ve