代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/284171/8957838
vhd commcore.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity benif_32reg_24bmem is
port (
-- Interface clock.
CLK: in STD_LOGIC;
-- Global reset.
www.eeworm.com/read/427067/8978995
vhd bcdconvtb.vhd
--
-- Copyright (C) Doulos Ltd 2001
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use STD.textio.all;
entity BCDConvTB is
end;
architecture Bench of BCDConvTB is
www.eeworm.com/read/427067/8979000
vhd bcdconv.vhd
--
-- Copyright (C) Doulos Ltd 2001
--
library IEEE;
use IEEE.std_logic_1164.all;
entity BCDConv is
generic (N : positive); -- number of digits
port (Clock : in std_logic;
www.eeworm.com/read/185843/8981742
txt vhdl-ysw.txt
第一个CNT60实现秒钟计时功能，第二个CNT60实现分钟的计时功能，CTT3完成两小时的计时功能。秒钟计时模块的进位端和开关K1相与提供分钟的计时模块使能，当秒种计时模块计时到59时向分种计时模块进位，同时自己清零。同理分种计时模块到59时向CTT3小时计时模块进位，到1小时59分59秒时，全部清零。同时，开关K1可以在两小时内暂停秒钟计时模块，分钟计时模块和小时计时模块。各模块的VHDL语言描 ...
www.eeworm.com/read/185746/8987867
vhd ball.vhd
--乒乓球灯模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ball is
port(clk:in std_logic;--乒乓球灯前进时钟
clr:in std_logic;--乒乓球灯清零
way:in std_logic;--乒乓球灯前进方向
en
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vhd gh_mac_16bit_ld.vhd
-----------------------------------------------------------------------------
-- Filename: gh_MAC_16bit_ld.vhd
--
-- Description:
-- Multiply Accumulator
-- the total gain must be 1 or less
-
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vhd gh_mult_ip_usus_mg.vhd
-----------------------------------------------------------------------------
-- Filename: gh_mult_ip_usus_mg.vhd
--
-- Description:
-- an inplace multiplier unsigned inputs
-- with modif
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vhd usbcomm.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity USBcomm is
port(
--FPGA信号
A: in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
DIN: in STD_LOGIC_VECTOR(7 downto 0); -
www.eeworm.com/read/426738/9002481
vhd led.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LED is
port(
A : in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
WR : in STD_LOGIC; -- 写使能
DWR : in STD_LOGIC_VECTOR(
www.eeworm.com/read/426736/9002623
vhd txmittest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmittest is
port(
tx:out std_logic;
txclkout:out std_logic;--For test send clok;
data:in std_logic_vecto