usbcomm.vhd

USB与FPGA接口的程序设计。里面是所有的源文件都经本人测试可以用

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity USBcomm is
	port(
		--FPGA信号
		A:         in  STD_LOGIC_VECTOR(15 downto 0);     -- 地址总线
		DIN:       in  STD_LOGIC_VECTOR(7 downto 0);      -- 输入数据
		DOUT:      out STD_LOGIC_VECTOR(7 downto 0);      -- 输出数据
		DDRV:      out STD_LOGIC;                         -- 输出使能
		RD:        in  STD_LOGIC;                         -- 读
		WR:        in  STD_LOGIC;                         -- 写
		-- USB FIFO信号
		uc_adx:    out STD_LOGIC_VECTOR(2 downto 0);      -- 地址总线
		uc_drd:    in  STD_LOGIC_VECTOR(7 downto 0);      -- 读数据
		uc_dwr:    out STD_LOGIC_VECTOR(7 downto 0);      -- 写数据
		uc_wren:   out STD_LOGIC;                         -- 写使能
		-- USB控制器
		uc_ctrl:   out STD_LOGIC_VECTOR(7 downto 0);      -- 控制字
		uc_status: in  STD_LOGIC_VECTOR(7 downto 0);      -- 状态字
		uc_wrctrl: out STD_LOGIC;                         -- 控制写使能
		-- USB device地址
		uc_dadx:   out STD_LOGIC_VECTOR(6 downto 0);      -- device地址
		uc_wradx:  out STD_LOGIC                          -- 写使能
		);
end USBcomm;

architecture BHV of USBcomm is
	signal fifo: STD_LOGIC;
	signal ctrl: STD_LOGIC;
	signal dadx: STD_LOGIC;
begin
	
	-- 地址编码
	fifo<= '1' when A(15 downto 12)= "1110" else '0'; -- 0xExxx
	ctrl<= '1' when A(15 downto 12)= "1101" else '0'; -- 0xDxxx
	dadx<= '1' when A(15 downto 12)= "1100" else '0'; -- 0xCxxx
	
	DDRV<= '1' when (fifo= '1' or ctrl= '1' or dadx= '1') and rd= '0' else '0';
	
	-- fifo
	uc_adx   <= A(2 downto 0) when fifo= '1' else (others=> '-');
	DOUT     <= uc_drd when fifo= '1' and rd= '0' else (others=> 'Z');
	uc_dwr   <= DIN;
	uc_wren  <= '1' when fifo= '1' and wr= '0' else '0';
	
	-- 控制器
	uc_ctrl  <= DIN;
	DOUT     <= uc_status when ctrl= '1' and rd= '0' else (others=> 'Z');
	uc_wrctrl<= '1' when ctrl= '1' and wr= '0' else '0';
	
	-- USB device地址
	uc_dadx  <= DIN(6 downto 0);
	uc_wradx <= '1' when dadx= '1' and wr= '0' else '0';
	
end BHV;