commcore.vhd

来自「国外开源的一个片上网络系统的源代码」· VHDL 代码 · 共 164 行

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity benif_32reg_24bmem is
    port (
    	-- Interface clock.
        CLK: in STD_LOGIC;
        -- Global reset.
        RSTl: in STD_LOGIC;
        -- Indicates whether Spartan can receive data.
        BUSY: in STD_LOGIC;
        -- Indicates whether Spartan has data to send.
        EMPTY: in STD_LOGIC;
        -- Indicates that ADIO is address or data.
        AS_DSl: in STD_LOGIC;
        -- DMA engine is writing data out.
        DMA_WEN: in STD_LOGIC;
        -- DMA engine is reading data in.
        DMA_REN: in STD_LOGIC;
        -- Interrupt.
        INT: in STD_LOGIC;
        -- Read/Write enable.
        RENl_WENl: out STD_LOGIC;
        -- Indicates if Spartan is being read or being written to.
        RDl_WR: out STD_LOGIC;
        -- Interrupt to Spartan.
        INTl: out STD_LOGIC;
        -- Current active address.
        ADDRESS: out STD_LOGIC_VECTOR (30 downto 0);
        -- Write data into register.
        WRITE_STROBE: out STD_LOGIC;
        -- Read data from register.
        READ_STROBE: out STD_LOGIC;
        -- Current DMA count.
        COUNT: out STD_LOGIC_VECTOR (31 downto 0);
        -- Enable DMA engine.
        DMA_ENABLE: out STD_LOGIC;
        -- DMA direction.
        DMA_DIRECTION: out STD_LOGIC;
        -- DMA select.
        DMA_SEL: out STD_LOGIC_VECTOR (3 downto 0);
        -- DMA control is ready for DMA engine to send data.
        DMA_RDY: out STD_LOGIC;
        -- DMA control has data for DMA engin to read.
        DMA_DATA_AVAILABLE: out STD_LOGIC;
        -- Reset to rest of Virtex.
        RST: out STD_LOGIC;
        -- Synchronous reset.
        SYNC_RESET: out STD_LOGIC;
        -- DMA is reset.
        DMA_RESET: out STD_LOGIC;
        -- Data IO between Spartan and Virtex.
        ADIO: inout STD_LOGIC_VECTOR (31 downto 0);
        -- Internal data bus.
        DATA: inout STD_LOGIC_VECTOR (31 downto 0);
        -- Internal DMA data bus.
        DMA_DATA: inout STD_LOGIC_VECTOR (31 downto 0)      
        );  
end benif_32reg_24bmem;

architecture arch of benif_32reg_24bmem is

component SV_IFACE
    generic (-- Number of memory blocks in memory map in bit size.
    		NUM_BLOCKSg : integer range 1 to 29;-- := 4;
    		-- Block size.
    		BLOCK_SIZEg : integer range 1 to 29;--:= 8;
    		-- Number of registers.
    		NUM_REGSg : integer range 1 to 29-- := 4
    		);
    port (
    	-- Interface clock.
        CLK: in STD_LOGIC;
        -- Global reset.
        RSTl: in STD_LOGIC;
        -- Indicates whether Spartan can receive data.
        BUSY: in STD_LOGIC;
        -- Indicates whether Spartan has data to send.
        EMPTY: in STD_LOGIC;
        -- Indicates that ADIO is address or data.
        AS_DSl: in STD_LOGIC;
        -- DMA engine is writing data out.
        DMA_WEN: in STD_LOGIC;
        -- DMA engine is reading data in.
        DMA_REN: in STD_LOGIC;
        -- Interrupt.
        INT: in STD_LOGIC;
        -- Read/Write enable.
        RENl_WENl: out STD_LOGIC;
        -- Indicates if Spartan is being read or being written to.
        RDl_WR: out STD_LOGIC;
        -- Interrupt to Spartan.
        INTl: out STD_LOGIC;
        -- Current active address.
        ADDRESS: out STD_LOGIC_VECTOR (30 downto 0);
        -- Write data into register.
        WRITE_STROBE: out STD_LOGIC;
        -- Read data from register.
        READ_STROBE: out STD_LOGIC;
        -- Current DMA count.
        COUNT: out STD_LOGIC_VECTOR (31 downto 0);
        -- Enable DMA engine.
        DMA_ENABLE: out STD_LOGIC;
        -- DMA direction.
        DMA_DIRECTION: out STD_LOGIC;
        -- DMA select.
        DMA_SEL: out STD_LOGIC_VECTOR (3 downto 0);
        -- DMA control is ready for DMA engine to send data.
        DMA_RDY: out STD_LOGIC;
        -- DMA control has data for DMA engin to read.
        DMA_DATA_AVAILABLE: out STD_LOGIC;
        -- Reset to rest of Virtex.
        RST: out STD_LOGIC;
        -- Synchronous reset.
        SYNC_RESET: out STD_LOGIC;
        -- DMA is reset.
        DMA_RESET: out STD_LOGIC;
        -- Data IO between Spartan and Virtex.
        ADIO: inout STD_LOGIC_VECTOR (31 downto 0);
        -- Internal data bus.
        DATA: inout STD_LOGIC_VECTOR (31 downto 0);
        -- Internal DMA data bus.
        DMA_DATA: inout STD_LOGIC_VECTOR (31 downto 0)
    );
end component;

begin
  
benif : SV_IFACE 
		generic map (	NUM_BLOCKSg => 1,
    				BLOCK_SIZEg => 24,
    				NUM_REGSg => 5
    				)
		port map ( 
          CLK => CLK,
          RSTl => RSTl,
          BUSY => BUSY,
          EMPTY => EMPTY,
          AS_DSl => AS_DSl,
          DMA_WEN => DMA_WEN,
          DMA_REN => DMA_REN,
          INT => INT,
          RENl_WENl => RENl_WENl,
          RDl_WR => RDl_WR,
          INTl => INTl,
          ADDRESS => ADDRESS,
          WRITE_STROBE => WRITE_STROBE,
          READ_STROBE => READ_STROBE,
          COUNT => COUNT,
          DMA_ENABLE => DMA_ENABLE,
          DMA_DIRECTION => DMA_DIRECTION,
          DMA_SEL => DMA_SEL,
          DMA_RDY => DMA_RDY,
          DMA_DATA_AVAILABLE => DMA_DATA_AVAILABLE,
          RST => RST,
          SYNC_RESET => SYNC_RESET,
          DMA_RESET => DMA_RESET,
          ADIO => ADIO,
          DATA => DATA,
          DMA_DATA => DMA_DATA
        );
end arch;