代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
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vhd myregslibrary.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package myregslibrary is
constant size : integer := 16;
component rdff
port (clk,reset : in std_logic;
d
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vhd uart_5kvg_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
www.eeworm.com/read/383549/8936335
vhd uart_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
www.eeworm.com/read/186331/8944954
vhd ch4_6_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ch4_6_1 is
port(
dataout:out std_logic_vector(6 downto 0);
addr :in
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txt 只读存储器.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ch4_6_1 is
port(
dataout:out std_logic_vector(6 downto 0);
addr :in
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vhd reg_8rst.vhd
-- "reg_8rst.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gene
www.eeworm.com/read/383392/8950652
vhd reg_pc.vhd
-- "reg_pc.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Genera
www.eeworm.com/read/383392/8950711
vhd reg_s.vhd
-- "reg_s.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General
www.eeworm.com/read/383392/8950718
vhd reg_8t.vhd
-- "reg_8t.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Genera
www.eeworm.com/read/427328/8951139
vhd dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLKK : IN STD_LOGIC;
FWORD