代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/291453/8417554
vhd 加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
www.eeworm.com/read/291453/8417557
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/291453/8417590
vhd 相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/391071/8422323
vhd alaw_l_nl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity alaw_l_nl is
port(
data :in std_logic_vector(12 downto 0); --pcm linear signal
clock :in std_logic; --system clock
fram
www.eeworm.com/read/391002/8428622
txt miaobiao.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity keyin is
port(reset,start_stop,clk :in std_logic;
res,stst :out std_logic);
end entity;
architec
www.eeworm.com/read/390924/8433387
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/190618/8439946
c cpsupp.c
/*************************************************************
* File: lib/cpsupp.c
* Purpose: Part of C runtime library
* Author: Phil Bunce (pjb@carmel.com)
* Revision History:
* 970304 Start o
www.eeworm.com/read/390486/8462573
vhd counter10.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
Port ( clk : in std_logic;
reset : in std_logic;
www.eeworm.com/read/390486/8462737
vhd counter24.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter24 is
Port ( clk : in std_logic;
reset : in std_logic;
www.eeworm.com/read/390455/8464808
vhd wblkzq.vhd
--WBLKZQ
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY WBLKZQ IS
PORT( RESET,SET_T,START,TEST,CLK,clk0: IN STD_LOGIC;
DA