wblkzq.vhd

来自「eda微波炉程序控制器 初学vhdl语言的控制程序设计」· VHDL 代码 · 共 147 行

--WBLKZQ

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY WBLKZQ IS
  PORT( RESET,SET_T,START,TEST,CLK,clk0: IN STD_LOGIC;
		DATA0:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		COOK : OUT STD_LOGIC;
		SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
		DISPLAY:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
		);
END ENTITY WBLKZQ;
ARCHITECTURE A OF WBLKZQ IS
 
  SIGNAL K_LD_8888,K_LD_CLK,K_LD_DONE,K_COOK:STD_LOGIC;
  SIGNAL Z_DATA2:STD_LOGIC_VECTOR(15 DOWNTO 0);
  SIGNAL Z_LOAD:STD_LOGIC;
  SIGNAL J_SEC_L,J_SEC_H,J_MIN_L,J_MIN_H:STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL J_DONE:STD_LOGIC;
  SIGNAL Y_SEC_L,Y_SEC_H,Y_MIN_L,Y_MIN_H:STD_LOGIC_VECTOR(6 DOWNTO 0);

COMPONENT KZQ IS 
  PORT(RESET,SET_T,START,TEST,CLK,DONE: IN STD_LOGIC;
       COOK,LD_8888,LD_CLK,LD_DONE:OUT STD_LOGIC);
END COMPONENT;
COMPONENT ZZQ IS
  PORT(DATA1: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
       LD_8888 : IN STD_LOGIC;
       LD_CLK  : IN STD_LOGIC;
	   LD_DONE : IN STD_LOGIC;
       DATA2   : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
       LOAD	   : OUT STD_LOGIC);
 END COMPONENT;
COMPONENT JSQ IS  
  PORT(COOK  : IN STD_LOGIC;
       DATA3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
       LOAD  : IN STD_LOGIC;
       CLK   : IN STD_LOGIC;
       SEC_L : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
       SEC_H : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
       MIN_L : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
       MIN_H : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
       DONE  : OUT STD_LOGIC);
END  COMPONENT;
COMPONENT YMQ47 IS
   PORT(AIN4  : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        DOUT7 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;

COMPONENT XIANSHI IS
  PORT(CLK0 : IN STD_LOGIC;
       SEC_L,SEC_H,MIN_L,MIN_H : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
       SEL: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
       DISPLAY : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
       
BEGIN
U1:KZQ PORT MAP(RESET,SET_T,START,TEST,CLK,J_DONE,K_LD_8888,K_LD_CLK,K_LD_DONE);
U2:ZZQ PORT MAP(DATA0(15 DOWNTO 0),K_LD_8888,K_LD_CLK,K_LD_DONE,Z_DATA2(15 DOWNTO 0),Z_LOAD);
U3:JSQ PORT MAP(K_COOK,Z_DATA2(15 DOWNTO 0),Z_LOAD,CLK,J_SEC_L(3 DOWNTO 0),J_SEC_H(3 DOWNTO 0),J_MIN_L(3 DOWNTO 0),J_MIN_H(3 DOWNTO 0),J_DONE);
U8:YMQ47 PORT MAP(J_SEC_L(3 DOWNTO 0),Y_SEC_L(6 DOWNTO 0));
U9:YMQ47 PORT MAP(J_SEC_H(3 DOWNTO 0),Y_SEC_H(6 DOWNTO 0));
F6:YMQ47 PORT MAP(J_MIN_L(3 DOWNTO 0),Y_MIN_L(6 DOWNTO 0));
F7:YMQ47 PORT MAP(J_MIN_H(3 DOWNTO 0),Y_MIN_H(6 DOWNTO 0));
F8:XIANSHI PORT MAP(CLK0,Y_SEC_L(6 DOWNTO 0),Y_SEC_H(6 DOWNTO 0),Y_MIN_L(6 DOWNTO 0),Y_MIN_H(6 DOWNTO 0),SEL,DISPLAY(6 DOWNTO 0));
COOK<=K_COOK;
END A;