代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/211745/15174419
vhd rxcver.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity RXCVER is
--generic:constant:std_logic;
port
www.eeworm.com/read/211745/15174441
vhd mul3.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mul3 is
port(in1,in2,in3:std_logic_vector(7 downto 0);
sela,selb,selc:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
e
www.eeworm.com/read/211745/15174509
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/211745/15174516
vhd counter100.vhd
--counter100
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter100 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/211745/15174531
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/211745/15174538
vhd counter100.vhd
--counter100
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter100 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/211745/15174576
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/211745/15174701
vhd counter_1024.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_1024 is
port(clk,clr,en,updn,bcdwr:in std_logic;
datain:in std_logic_vector(9 downt
www.eeworm.com/read/211218/15184637
vhd cal_ctl.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
entity cal_ctl is
p
www.eeworm.com/read/210918/15189905
vhd pll.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pll is
port(clk_in,data_in : in std_logic;
clk_out,state,data_ou