counter60.vhd

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--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
 port(clk,clr:in std_logic;
        c:out std_logic;
      bcd1:out std_logic_vector(3 downto 0);
      bcd2:out std_logic_vector(3 downto 0));
end counter60;

architecture rtl of counter60 is
 signal bcd1n:std_logic_vector(3 downto 0):="0000";
 signal bcd2n:std_logic_vector(3 downto 0):="0000";
 signal cn:std_logic:='1';
begin
 bcd1<=bcd1n;
 bcd2<=bcd2n;
    c<=cn; 
 process(clk)
    begin
   if(clr='0') then
     bcd1n<="0000";
   else
     if(clk'event and clk='0') then
       if(bcd1n="1001") then
          bcd1n<="0000";
        else
         bcd1n<=bcd1n+1;
       end if;
     end if;
    end if;
end process;
 process(clk)
   begin
   if(clr='0') then
     bcd2n<="0000";  
   else
    if(clk'event and clk='0') then
       if(bcd1n="1001") then
          if(bcd2n="0101") then
            bcd2n<="0000";
           else
            bcd2n<=bcd2n+1;
           end if;
        end if;
     end if;
   end if;
end process;
process(clk)
   begin
     if(clk'event and clk='0') then
       if(bcd1n="1001" and bcd2n="0101") then
       cn<='0';
       else
       cn<='1';
       end if;
     end if;
end process;
end rtl;