pll.vhd

VHDL程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pll is
    port(clk_in,data_in         : in  std_logic;
         clk_out,state,data_out : out std_logic);
end entity pll;

architecture pll_a of pll is
    signal cnt1      : std_logic_vector (4 downto 0):="00000";
    signal clk       : std_logic:='0';

    signal data_delay: std_logic;
    signal en        : std_logic:='0';

    signal t0        : std_logic_vector (18 downto 0):="0000000000000000000";
    signal t1        : std_logic_vector (17 downto 0):="111111111111111111";
    signal t2        : std_logic_vector (17 downto 0):="000000000000000000";

    signal num1      : std_logic_vector (5 downto 0);
    signal num2      : std_logic_vector (5 downto 0);

    signal cnt       : std_logic_vector (5 downto 0):="000000"; 	
    signal add       : std_logic:='0';
    signal dec       : std_logic:='0';

begin
    data_out<=data_in;
    
    process(clk_in)
    begin
        if (clk_in'event and clk_in='1') then
           if (cnt1="11000")then
               clk<=not clk;
               cnt1<="00000";
           else 
               cnt1<=cnt1+'1';
           end if;
        end if;
    end process;

    process(clk_in)
    begin
        if (clk_in'event and clk_in='1') then
            data_delay<=data_in;
        end if;
        en<=data_delay xor data_in;
    end process;

    process(clk_in)
    begin
	if (clk_in'event and clk_in='1') then
	    t0<=t0+'1';
	end if;
    end process;

    process(clk_in)
    begin
        if (clk_in'event and clk_in='1' and t0<"1100000000000000000") then
	    t2<=t2+'1';
            if (en='1' and t1>t2) then
		t1<=t2;
	        t2<="000000000000000000";
	    end if;
	end if;
    end process;

    process(clk_in)
    begin
        if (clk_in'event and clk_in='1') then
	    if (t0>="1100000000000000000") then
		if (t1<"1000000000") then
		    num1<="000111";
		    num2<="001110";
		elsif (t1>"1000000000" and t1<"10000000000") then
		    num1<="001110";
		    num2<="011101";
		else
		    num1<="011101"; 
		    num2<="111011";
		end if;
	    end if;
        end if;
    end process;
	        

    process(clk_in)
    begin
	 if (t0<="1100000000000000000") then
	     state<='0'; 		
        elsif (clk_in'event and clk_in='1' and t0>"1100000000000000000") then
            if(en='1') then
	             if (cnt<num2)and(cnt>=num1) then
		              add<='1';
		              
		          elsif (cnt<num1)and(cnt>"000001") then
                    dec<='1';
                else
                    state<='1';
                end if;
               
                    
            end if;
         
            if (cnt1="00000") then  
                if(add='1') then
 		              cnt<=cnt+"000011";
                    add<='0';
		    
                elsif(dec='1') then
                    cnt<=cnt-"000001";
	                 dec<='0';
                else         
		              cnt<=cnt+'1';
                end if;

                if (cnt=num1) then
                    clk_out<='0';
                elsif (cnt=num2) then
                    clk_out<='1';
                    cnt<="000000";
	             elsif (cnt>num2) then
                    clk_out<='1';
                    cnt<="000001";
                end if;
            end if;
	     end if;
    end process;

end architecture pll_a;