代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/255821/12055527
txt 超前进位加法器.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity add_n is
generic
(
n:integer:=8
);
port
(
cin:in std_logic;
cout:out std_logic;
a,b: in std_
www.eeworm.com/read/255779/12056401
vhd keymem_struct.vhd
-------------------------------------------------------------------------------
-- --
-- AES86 - VHDL 128bits AES IP Core
www.eeworm.com/read/153105/12060238
vhd regfile.vhd
--****************************************************************************************************
-- Register file for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 23.01.2003
--******
www.eeworm.com/read/153105/12060270
vhd alu.vhd
--****************************************************************************************************
-- ALU for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 16.12.2002
--****************
www.eeworm.com/read/153105/12060282
vhd controllogic.vhd
--****************************************************************************************************
-- Control logic for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 04.02.20
www.eeworm.com/read/153105/12060314
vhd bbusmultiplexer.vhd
--****************************************************************************************************
-- B bus multiplexer for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 04.1
www.eeworm.com/read/153105/12060337
vhd datamux.vhd
--****************************************************************************************************
-- Data multiplexer for ARM memory sybsistem
-- Designed by Ruslan Lepetenok
-- Modified 07.12
www.eeworm.com/read/255474/12079075
vhd arbitrate.vhd
--本程序是Sdram控制器中的裁决部分，完成外部的6个随机请求按时间顺序排列，并保证信号的完整性
--从而控制后续的状态机发出特定的Sdram命令序列
--输入：
-- SdramClk Sdram时钟，100MHz
-- ResetGlb 全局复位
-- FIFO1AlmostF 前端Fifo几乎满信号，高电平有效
-- FIFO2AlmostE 后端FIFO几乎空信号，低电平有
www.eeworm.com/read/255041/12104316
vhd vgarom.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity vgarom is
port ( CLK1 : in STD_LOGIC;
A18 : out STD_LOGIC;
OE1 : out STD_LOGIC;
www.eeworm.com/read/255039/12104507
vhd cnta.vhd
LIBRARY IEEE; -- 24进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNTA IS
PORT ( CLK : IN STD_LOGIC;
U_D : IN STD_LO