vgarom.vhd

基于fpga和sopc的用VHDL语言编写的EDA的VGA图像显示控制器

library IEEE;
use IEEE.std_logic_1164.all;	  
use	IEEE.std_logic_unsigned.all;

entity vgarom is
	port ( CLK1 :  in STD_LOGIC;
        A18  : out STD_LOGIC;
        OE1  : out STD_LOGIC;
 

        clk: in STD_LOGIC;
		r: out STD_LOGIC;
		g: out STD_LOGIC;
		b: out STD_LOGIC;
		hs: out STD_LOGIC;
		vs: out STD_LOGIC;
		addr: out STD_LOGIC_VECTOR (17 downto 0);
		--ce: out STD_LOGIC;
		oe: out STD_LOGIC;
		data8: in STD_LOGIC_VECTOR (7 downto 0);
		modf: in STD_LOGIC
	);
end vgarom;

--}} End of automatically maintained section

architecture behv of vgarom is			 
signal	tr,tg,tb	:	std_logic;				  
signal	ck	:	std_logic;
signal	hcnt	:	std_logic_vector(9 downto 0);
signal	vcnt	:	std_logic_vector(8 downto 0);

signal	hs1	:	std_logic;
signal	vs1	:	std_logic;
signal	DV1	:	std_logic;

begin
  OE1 <= '1';
  -- <<enter your statements here>>	 
process(CLK1)		 
	begin
		if(CLK1'event and CLK1 = '1') then
			 DV1 <= NOT DV1;
		end if;
      A18 <= DV1 ;
end	process;

process(clk)  
	begin
	if(clk'event and clk = '1') then  
			ck <= not ck;
		end if;
end process;

oe <=  '0' ;

process(ck)		 
	begin
		if(ck'event and ck = '1') then
			if(hcnt >= 800-1)	then
				hcnt <= "0000000000";
			else	hcnt <= hcnt + 1;
			end if;					  
	end if;
end	process;

process(ck)
begin
	if(ck'event and ck = '1') then
		if(hcnt >= 640)	then
				hs1 <= '1';
			else	hs1 <= '0';
		end if;	
	end if;
end process;

process(hs1)
begin
	if(hs1'event and hs1 = '1') then			   
		if(vcnt >= 482-1)	then
			vcnt <= "000000000";
		else	vcnt <= vcnt + 1;
		end if;
	end if;
end process;

process(hs1)
begin
	if(hs1'event and hs1 = '1')	then
		if(vcnt >= 480)	then
			vs1 <= '1';
		else	vs1 <= '0';
		end if;
	end if;
end process;

addr <= vcnt * "101000000" + hcnt(9 downto 1);

process(ck)
begin
	if(ck'event and ck = '0')	then
		if(hcnt(0) = '0')	then
				tr <= modf xor data8(1);
				tg <= modf xor data8(2);
				tb <= modf xor data8(3);
		else
				tr <= modf xor data8(5);
				tg <= modf xor data8(6);
				tb <= modf xor data8(7);
		end if;						
	end if;
end process;
		
r <= tr and (not hs1) and (not vs1);
g <= tg and (not hs1) and (not vs1);
b <= tb and (not hs1) and (not vs1);

hs <= hs1;
vs <= vs1;
end behv;