📄 keymem_struct.vhd
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-------------------------------------------------------------------------------
-- --
-- AES86 - VHDL 128bits AES IP Core --
-- Copyright (C) 2005-2007 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-- AES86 is released as open-source under the GNU GPL license. This means --
-- that designs based on AES86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY keymem IS
PORT(
addrmux : IN std_logic;
addrmux0 : IN std_logic_vector (3 DOWNTO 0);
addrmux1 : IN std_logic_vector (3 DOWNTO 0);
clk : IN std_logic;
din128 : IN std_logic_vector (127 DOWNTO 0);
we : IN std_logic;
dout128 : OUT std_logic_vector (127 DOWNTO 0)
);
-- Declarations
END keymem ;
ARCHITECTURE struct_sync OF keymem IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL addr : std_logic_vector(3 DOWNTO 0);
-- Component Declarations
COMPONENT ssram
PORT (
addr : IN std_logic_vector (3 DOWNTO 0);
clk : IN std_logic ;
din128 : IN std_logic_vector (127 DOWNTO 0);
we : IN std_logic ;
dout128 : OUT std_logic_vector (127 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- ModuleWare code(v1.7) for instance 'I1' of 'mux'
i1combo_proc: PROCESS(addrmux0, addrmux1, addrmux)
BEGIN
CASE addrmux IS
WHEN '0' => addr <= addrmux0;
WHEN '1' => addr <= addrmux1;
WHEN OTHERS => addr <= (OTHERS => '0');
END CASE;
END PROCESS i1combo_proc;
-- Instance port mappings.
I0 : ssram
PORT MAP (
addr => addr,
clk => clk,
din128 => din128,
we => we,
dout128 => dout128
);
END struct_sync;
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