代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
www.eeworm.com/read/173140/9671051
m ss_mlsrs.m
function [seq]=ss_mlsrs(connections);
% [seq]=ss_mlsrs(connections)
% SS_MLSRS generates the maximal length shift register sequence when the
% shift register connections are given as input to th
www.eeworm.com/read/172852/9685928
c example_281xadcseq_ovdtest.c
//###########################################################################
//
// FILE: Example_281xAdcSeq_ovdTest.c
//
// TITLE: DSP281x ADC Seq Override mode Test.
//
// ASSUMPTIONS:
//
www.eeworm.com/read/171426/9756571
c ref_norm.c
/* ____________________________________________________________________
*
* Copyright (c) 2003, Andrew N. Sloss, Dominic Symes, Chris Wright
* All rights reserved.
* __________________________
www.eeworm.com/read/367095/9783185
faq
Frequently Asked Questions
----------------------------------------------------------------------------
Is it possible not to use pthreads library?
Yes, it is possible. J
www.eeworm.com/read/415959/11046720
m normalise.m
function im2 = normalise(im)
% linear shift + scale
% to fit from 0 to 1
im2 = im - min(min(min(im)));
if (max(max(max(im2))) ~= 0)
im2 = im2 / max(max(max(im2)));
end
www.eeworm.com/read/269573/11091523
h misc.h
/********************************************************************
* *
* THIS FILE IS PART OF THE OggVorbis 'TREMOR' CODEC SOURCE
www.eeworm.com/read/268231/11149123
m ss_mlsrs.m
function [seq]=ss_mlsrs(connections);
% [seq]=ss_mlsrs(connections)
% SS_MLSRS generates the maximal length shift register sequence when the
% shift register connections are given as input to th
www.eeworm.com/read/413318/11159662
v seq_div.v
module seq_div(clk, rst, load, dividend, divisor, overflow,
done, quotient, remainder);
parameter WidthDividend = 11, // 被除数位宽
WidthDivisor = 6, // 除数位宽
WidthCount = 3;
input clk,
www.eeworm.com/read/412328/11204421
v shiftreg.v
module shift_reg(shiftreg,clock,reset,load,sel,data);
input clock;
input reset;
input load;
input [1:0] sel;
input [4:0] data;
output[4:0] shiftreg;
reg [4:0] shiftreg;
always @(posedge clock)
begin
www.eeworm.com/read/412298/11206715
vhd shifter.vhd
-- Description : right shifts a 64 bit value i places
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;