seq_div.v

a divider design based on verilog language

module seq_div(clk, rst, load, dividend, divisor, overflow,
				done, quotient, remainder);
	parameter 	WidthDividend = 11,	// 被除数位宽
				WidthDivisor = 6,		// 除数位宽
				WidthCount = 3;
	input clk, rst, load;
	input [WidthDividend-1:0] 	dividend;
	input [WidthDivisor-1:0]	divisor;
	output	overflow, done;
	output[WidthDividend-WidthDivisor-1:0] quotient;
	output[WidthDivisor-1:0] remainder;
	reg  	overflow, done;
	
	// FSM 状态机
	parameter 	ST_WAIT 	= 0,
				ST_SHIFT 	= 1,
				ST_OVERFLOW = 2,
				ST_SUBTRACT	= 3,
				ST_DONE		= 4;
	reg [2:0]  				CurrentState, NextState;
	reg [WidthCount-1:0]	CurrentCount, NextCount;
	reg Shift, Subtract, A_GE_B;
	
	reg QuoRemSign;
	reg [WidthDivisor-2:0] RegA, RegB, notRegB;
	reg [WidthDividend-WidthDivisor-1:0] RegQ;
	reg [WidthDivisor-2:0] RegA_minus_RegB;
	
	// FSM状态生成
	always @(load or A_GE_B or CurrentCount or CurrentState)begin
		Shift = 0;
		Subtract = 0;
		overflow = 0;
		done = 0;
		NextCount = CurrentCount;
		case(CurrentState)
			ST_WAIT: begin
				NextCount = WidthDivisor - 1;
				if(load)begin
					Shift = 1;
					NextState = ST_SHIFT;
				end
				else
					NextState = ST_WAIT;
			end
			ST_SHIFT: begin
				if((CurrentCount == (WidthDivisor - 1))&&A_GE_B)begin
					overflow = 1;
					NextState =ST_OVERFLOW;
				end
				else if(CurrentCount == 0)begin
					done = 1;
					NextState = ST_DONE;
				end
				else if(A_GE_B)begin
					Subtract = 1;
					NextState = ST_SUBTRACT;
				end
				else begin
					Shift = 1;
					NextCount = CurrentCount -1;
					NextState = ST_SHIFT;
				end
			end
			ST_OVERFLOW:if(load)begin
					Shift = 0;
					NextCount = WidthDivisor - 1;
					NextState = ST_SHIFT;
				end
				else begin
					overflow = 1;
					NextState = ST_OVERFLOW;
				end
			ST_SUBTRACT: begin
					Shift = 1;
					NextCount = CurrentCount - 1;
					NextState = ST_SHIFT;
				end
			ST_DONE:if(load)begin
					Shift = 1;
					NextCount = WidthDivisor - 1;
					NextState = ST_SHIFT;
				end
				else begin
					done = 1;
					NextState = ST_DONE;
				end
			default: NextState = CurrentState;
		endcase
	end
	
	always @(posedge clk)begin:FSM_SEQ
		if(rst)begin
			CurrentCount = WidthDivisor -2;
			CurrentState = ST_WAIT;
		end
		else begin
			CurrentCount = NextCount;
			CurrentState = NextState;	
		end
	end
	
	// Compare (RegA - RegB)
	always @(RegA or RegB)begin
		notRegB = ~RegB;
		{A_GE_B,RegA_minus_RegB} = RegA + notRegB + 1;
	end
	
	// Data registers
	always @(posedge clk)begin
		if(rst)begin	// reset
			RegA = 0;
			RegQ = 0;
			RegB = 0;
		end
		else if(load)begin	// load
			QuoRemSign = dividend[WidthDividend-1]^
						 divisor[WidthDivisor-1];
			{RegA, RegQ} = dividend[WidthDividend-2:0];
			RegB = divisor[WidthDivisor-2:0];
		end
		else if(Shift)	// shift
			{RegA, RegQ} = {RegA, RegQ} << 1;
		else if(Subtract)begin	// subtract
			RegQ[0] = A_GE_B;
			RegA = RegA_minus_RegB;
		end
	end
	
	assign quotient = {QuoRemSign, RegQ};
	assign remainder = {QuoRemSign, RegA};
endmodule