代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
www.eeworm.com/read/443856/7621817
vhd shift_register.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity shift_register is
-- 类属参数
generic (
TOTAL_BIT : integer := 10 );
-- 端口
port (
clk : in std_logic;
reset_n : in std_lo
www.eeworm.com/read/440903/7679035
v shift_register.v
`timescale 1ns/1ns
module shift_register(data_out,data_in,din,rst,load,opcode,clk);
output[7:0] data_out;
input[7:0] data_in;
input din,rst,load,opcode,clk;
reg[7:0] data_out;
reg[7
www.eeworm.com/read/440644/7684817
m shift_ifft.m
% File: shift_ifft.m
% Software given here is to accompany the textbook: W.H. Tranter,
% K.S. Shanmugan, T.S. Rappaport, and K.S. Kosbar, Principles of
% Communication Systems Simulation with Wir
www.eeworm.com/read/440553/7687765
v shift_reg.v
// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likel
www.eeworm.com/read/439761/7701941
vhd shift8.vhd
-- ************************************************************************
-- File: shift8.vhd
--
-- Purpose: Serial in/serial out 8-bit parallel load/out shift
-- register comp
www.eeworm.com/read/439761/7701950
vhd shift16.vhd
-- ************************************************************************
-- File: shift16.vhd
--
-- Purpose: Serial in/serial out 16-bit parallel load/out shift
-- register co
www.eeworm.com/read/439401/7710313
m shift_ifft.m
% File: shift_ifft.m
% Software given here is to accompany the textbook: W.H. Tranter,
% K.S. Shanmugan, T.S. Rappaport, and K.S. Kosbar, Principles of
% Communication Systems Simulation with Wir
www.eeworm.com/read/438480/7730870
inc shift_register.inc
--Copyright (C) 1991-2003 Altera Corporation
--Any megafunction design, and related netlist (encrypted or decrypted),
--support information, device programming or simulation file, and any oth