shift_register.v

用Verilog实现的移位寄存器

`timescale 1ns/1ns
module shift_register(data_out,data_in,din,rst,load,opcode,clk);
   
   output[7:0] data_out;
   input[7:0] data_in;
   input din,rst,load,opcode,clk;
   reg[7:0] data_out;
   reg[7:0] data_temp;
   
   always@(posedge clk or negedge rst)
     if(!rst) 
       data_out=0;
     else
     begin
       if(load) 
         data_temp=data_in;
       else 
         if(!opcode)
           data_temp={data_temp[6:0],din}; 
         else
           data_temp={din,data_temp[7:1]};  
       data_out=data_temp;
     end
   
endmodule