shift_reg.v

来自「FPGA Cycloneii 系列的」· Verilog 代码 · 共 67 行

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
// Created on Sat Jun 30 10:16:53 2007

//  Module Declaration
module shift_reg
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	clk, reset_n, din, dout, regs_out, parity_out
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input clk;
	input reset_n;
	input din;
	output dout;
	output [7:0] regs_out;
	output parity_out;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
    reg [10:0]shift_out;
	reg dout;
	
	assign regs_out[0]=shift_out[8];
	assign regs_out[1]=shift_out[7];
	assign regs_out[2]=shift_out[6];
	assign regs_out[3]=shift_out[5];
	assign regs_out[4]=shift_out[4];
	assign regs_out[5]=shift_out[3];
	assign regs_out[6]=shift_out[2];
	assign regs_out[7]=shift_out[1];
								
	assign parity_out=shift_out[1];
	
	always@ (posedge clk or negedge reset_n)
		if(reset_n==1'b0)
			dout<=1'b1;
		else 
			begin
				dout<=shift_out[10];
				shift_out[10:1]<=shift_out[9:0];
				shift_out[0]<=din;
			end



endmodule