代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
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tdf shift_pll_inst.tdf
(
c0_sig,
c1_sig,
c2_sig,
locked_sig
) = shift_pll (
.inclk0 = inclk0_sig
)
RETURNS (
.c0,
.c1,
.c2,
.locked
);
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vwf shift_clk-sim.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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msg shift_clk.csf.msg
{ Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf " "Found 1 design units and 1 entities in
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msg shift_clk.ssf.msg
{ Info "IDBC_ERROR_COUNT" "shift_clk Simulation was successful 0 s 0 s " "Design shift_clk: Simulation was successful. 0 errors, 0 warnings" { } { } }
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db_info shift_clk.db_info
Quartus_Version = Version 2.0 Build 204 03/26/2002 Service Pack 1 SJ Full Version
Creation_Time = Thu Jun 20 09:00:30 2002
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hdb shift_clk.psf.hdb
www.eeworm.com/read/307021/13732913
vhd shift_circle2.vhd
LIBRARY IEEE;
USE ieee.std_logic_1164.all ;
ENTITY shift_circle2 IS
PORT(
clk : IN STD_logic; --时钟
ena : IN STD_logic; --移位使能
reset :
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bsf shift_r1.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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v shift_r1.v
/**************************************************
函数名：shift_r1
功 能：实现数据的串行输入并行输出
参数说明：clk 时钟
flag 标志信号，当完整接收到一个回答信号后则由此发出一个脉冲
data_in 输入的数据
dat
www.eeworm.com/read/141268/5774374
cpp integer_shift_instruction.cpp
/**
* Copyright (c) 2005 Zhejiang University, P.R.China
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as pu