shift_clk.csf.msg

vhdl编写的一个完整工程

{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf " "Found 1 design units and 1 entities in source file D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { Info "ISGN_ENTITY_NAME" "1 shift_clk " "Found entity 1: shift_clk" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "shift_clk" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { } } } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "0 0 D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.vwf " "Found 0 design units and 0 entities in source file D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.vwf" {  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_pll.tdf " "Found 1 design units and 1 entities in source file D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_pll.tdf" { { Info "ISGN_ENTITY_NAME" "1 shift_pll " "Found entity 1: shift_pll" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_pll.tdf" "shift_pll" "" { Text "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_pll.tdf" 40 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf " "Found 1 design units and 1 entities in source file D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" { { Info "ISGN_ENTITY_NAME" "1 altpll " "Found entity 1: altpll" {  } { { "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" "altpll" "" { Text "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" 268 1 0 } }  } }  } {  }  }
{  Info "ISCL_SCL_TM_SUMMARY" "9 " "Implemented 9 device resources" { { Info "ISCL_SCL_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } } { Info "ISCL_SCL_TM_OPINS" "4 " "Implemented 4 output pins" {  } {  } } { Info "ISCL_SCL_TM_LCELLS" "3 " "Implemented 3 logic cells" {  } {  } } { Info "ISCL_SCL_TM_PLLS" "1 " "Implemented 1 ClockLock PLLs" {  } {  } }  } {  }  }