shift_circle2.vhd

这是一些经典的vhdl example

LIBRARY IEEE; 
USE ieee.std_logic_1164.all ;
ENTITY shift_circle2 IS
	PORT(
		clk		: IN	STD_logic;                          --时钟
		ena		: IN	STD_logic;                          --移位使能
		reset	: IN	STD_logic;                          --异步复位
		q	    : OUT	STD_logic_vector(2 DOWNTO 0));      --寄存器输出
END shift_circle2;
ARCHITECTURE behavier OF shift_circle2 IS
	constant A: STD_logic_vector(2 downto 0):="001";		--定义状态编码
	constant B: STD_logic_vector(2 downto 0):="010";
	constant C: STD_logic_vector(2 downto 0):="100";
	SIGNAL present_state: STD_logic_vector(2 downto 0);
	SIGNAL next_state: STD_logic_vector(2 downto 0);
BEGIN
	update :PROCESS(reset, clk)			        --每个时钟上升沿，更新状态
    BEGIN
   	     IF (reset = '1') THEN 					--状态机复位
	 		present_state <= A;
	     ELSIF (clk'EVENT AND clk='1') THEN     --状态更新
	 		present_state <= next_state;
	     END IF;
    END PROCESS update;

	statedecoder:PROCESS(clk)					--状态译码
	BEGIN
		CASE present_state IS
			WHEN A =>
				IF ena='1' THEN
					next_state <= B;
				END IF;
			WHEN B =>
				IF ena='1' THEN
					next_state <= C;
				END IF;

			WHEN C =>
				IF ena='1' THEN
					next_state <= A;
				END IF;
			WHEN OTHERS =>						--多于状态处理
				next_state<=A;
		END CASE;
	END PROCESS statedecoder;
	q<=present_state;     --输出译码
END behavier;