代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
www.eeworm.com/read/14792/410944
vhd shift8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity shift8 is
port(a,clk1,clr1:in std_logic;
b:out std_logic);
end shift8;
architecture rtl of shift8 is
component dff4
port(clk,clr,d:in std_
www.eeworm.com/read/16498/673310
xco shift16.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c11
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/17522/734341
bit reg_shift.bit
www.eeworm.com/read/17522/734342
vhd reg_shift.vhd
--** 移位寄存器 **--
--文件名：reg_shift.vhd
--功 能：移位寄存器
--说 明：“data”采用八位拨盘开关来置入数据；
-- “q”中的数据每秒中移动一次，采用发光二极管来表示；
-- “enable”作为数据的输入使
www.eeworm.com/read/17522/734343
ucf reg_shift.ucf
NET "cs" LOC = "p175";
NET "cs" LOC = "p176";
NET "datain" LOC = "p110";
NET "datain" LOC = "p111";
NET "datain" LOC = "p112";
NET "datain" LOC = "p113";
NET "datain
www.eeworm.com/read/17578/739827
xco shift16.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c11
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/17609/742470
vhd shift_add.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity shift_add is
port(indata:in std_logic_vector(10 downto 0);
clk:in std_logic;
add_en: in std_logic;
www.eeworm.com/read/17609/742813
vhd shift8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity shift8 is
port(a,clk1,clr1:in std_logic;
b:out std_logic);
end shift8;
architecture rtl of shift8 is
component dff4
port(clk,clr,d:in std_
www.eeworm.com/read/17749/755392
bsf shift_clk.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/17749/755448
v shift_clk.v
module shift_clk(clkl,clkh,rst,clk_shift);
input clkl;
input clkh;
input rst;
output clk_shift;
reg clk_shift;
reg ttp;
always @(posedge clkh or negedge rst)
begin
if(!rst)
begin