shift_add.vhd

《CPLDFPGA嵌入式应用开发技术白金手册》源代码

library	ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all;

entity shift_add is
	port(indata:in std_logic_vector(10 downto 0);
	     clk:in std_logic;
	     add_en: in std_logic;
	     outdata:out unsigned(18 downto 0);
         rs:out std_logic);
end entity;

architecture beh of shift_add is
begin
main:process
variable old:unsigned(18 downto 0);
variable sum:unsigned(18 downto 0); 
variable sum1: unsigned(18 downto 0); 
variable sum2: unsigned(18 downto 0); 
variable sum3: unsigned(18 downto 0); 
variable sum4: unsigned(18 downto 0); 
variable sum5: unsigned(18 downto 0); 
variable sum6: unsigned(18 downto 0); 
variable sum7: unsigned(18 downto 0); 
variable temp:unsigned(10 downto 0);
variable count:unsigned(2 downto 0):="000";  
begin  
       wait until clk'event and clk='0'; 
       if add_en ='1' then
	   for i in 0 to 10 loop
            temp(i):=indata(i);
        end loop;
        case count is
		when
"000"=>old:=(temp(10)&temp(10)&temp(10)&temp(10)&temp(10)&temp(10)&temp(10)&temp(10)&temp(10 downto 0)); sum1:=old;

		when "001"=>old:=(temp(10)&temp(10)&temp(10)&temp(10)&temp(10)&temp(10)&temp(10)&temp(10 downto 0)&"0");sum2:=sum1+old;
		when "010"=>old:=(temp(10)&temp(10)&temp(10)&temp(10)&temp(10)&temp(10)&temp(10 downto 0)&"00");sum3:=sum2+old;
	   	when
"011"=>old:=(temp(10)&temp(10)&temp(10)&temp(10)&temp(10)&temp(10 downto 0)&"000");sum4:=sum3+old;
    		when
"100"=>old:=(temp(10)&temp(10)&temp(10)&temp(10)&temp(10 downto 0)&"0000");sum5:=sum4+old;
		when
"101"=>old:=(temp(10)&temp(10)&temp(10)&temp(10 downto 0)&"00000");sum6:=sum5+old;
		when
"110"=>old:=(temp(10)&temp(10)&temp(10 downto 0)&"000000");sum7:=sum6+old;  rs<='1';
		when 
"111"=>old:=(temp(10)&temp(10 downto 0)&"0000000");sum:=sum7+old;outdata<=sum;
		when 
others=>null;
end case;
count:=count+1;
end if;
 
end process;
end beh;