代码搜索：sdc
找到约 1,087 项符合「sdc」的源代码
代码结果 1,087
www.eeworm.com/read/142668/12931363
sdc not_and_sdc.sdc
# Top Level Design Parameters
# Clocks
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output
www.eeworm.com/read/425249/10367281
sdc connect_sdc.sdc
# Top Level Design Parameters
# Clocks
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output
www.eeworm.com/read/276507/10733425
sdc dds_sdc.sdc
# Top Level Design Parameters
# Clocks
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output
www.eeworm.com/read/467448/7012825
sdc dds_sdc.sdc
# Top Level Design Parameters
# Clocks
create_clock -period 8.384200 -waveform {0.000000 4.192100} clk
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constrai
www.eeworm.com/read/17603/740649
sdc main_sdc.sdc
# Top Level Design Parameters
# Clocks
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output
www.eeworm.com/read/17720/754718
sdc decoder_sdc.sdc
# Top Level Design Parameters
# Clocks
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output
www.eeworm.com/read/18421/787154
sdc top_sdc.sdc
# Top Level Design Parameters
# Clocks
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output
www.eeworm.com/read/18679/799753
sdc top_sdc.sdc
# Top Level Design Parameters
# Clocks
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output
www.eeworm.com/read/299888/3849719
sdc top_sdc.sdc
# Top Level Design Parameters
# Clocks
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output
www.eeworm.com/read/299888/3849732
sdc control_sdc.sdc
# Top Level Design Parameters
# Clocks
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output