top_sdc.sdc

来自「Allegro原理图和PCB」· SDC 代码 · 共 25 行

# Top Level Design Parameters

# Clocks


# False Paths Between Clocks


# False Path Constraints


# Maximum Delay Constraints


# Multicycle Constraints


# Virtual Clocks
# Output Load Constraints
# Driving Cell Constraints
# Wire Loads
# set_wire_load_mode top

# Other Constraints