代码搜索：out_data
找到约 581 项符合「out_data」的源代码
代码结果 581
www.eeworm.com/read/325191/13220771
lst 93c46.lst
C51 COMPILER V6.12 93C46 05/30/2008 14:02:14 PAGE 1
C51 COMPILER V6.12, COMPILATION OF MODULE 93C46
OBJECT MODULE PLACED IN .
www.eeworm.com/read/307038/13732341
c 93c46.c
#include
#include
//define OP code
#define OP_EWEN_H 0x00 // 00 write enable
#define OP_EWEN_L 0x60 // 11X XXXX write enable
#define OP_EWDS_H 0x00 // 00
www.eeworm.com/read/307038/13732347
lst 93c46.lst
C51 COMPILER V6.12 93C46 05/28/2005 21:58:03 PAGE 1
C51 COMPILER V6.12, COMPILATION OF MODULE 93C46
OBJECT MODULE PLACED IN .
www.eeworm.com/read/301619/13853847
c wl006.c
/*******************************************************************************
* 标题: ME300系列单片机开发系统演示程序 - AT93C46读写演示程序 *
* 硬件： ME300A+,ME300B
www.eeworm.com/read/301619/13853853
lst wl006.lst
C51 COMPILER V7.20 WL006 03/29/2005 15:45:49 PAGE 1
C51 COMPILER V7.20, COMPILATION OF MODULE WL006
OBJECT MODULE PLACED IN w
www.eeworm.com/read/408962/11363651
txt spi_testbench.txt
/*
SPI_Master_tb.v - Verilog source for SPI module Test Bench
Copyright (C) 2007 Steven Yu
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU
www.eeworm.com/read/406252/11445961
v select.v
module select(sel_1,msl_1,msh_1,sl_1,sh_1,out_data);
input[3:0] sel_1;
input[3:0] msl_1,msh_1,sl_1,sh_1;
output[3:0] out_data;
reg[3:0] out_data;
always @(sel_1)
begin
case(sel_1)
4'b0001
www.eeworm.com/read/259460/11789017
tcl bin2ram.tcl
#
# See the file "L2_RTI_EO1/disclaimers-and-notices-L2.txt" for
# information on usage and redistribution of this file,
# and for a DISCLAIMER OF ALL WARRANTIES.
#
# bin2ram.tcl - Binary To RAM Tcl
www.eeworm.com/read/345183/11831100
c 93c46.c
#include
#include
//define OP code
#define OP_EWEN_H 0x00 // 00 write enable
#define OP_EWEN_L 0x60 // 11X XXXX write enable
#define OP_EWDS_H 0x00 // 00