spi_testbench.txt

来自「SPI master的verilog代码」· 文本 代码 · 共 107 行

/*

SPI_Master_tb.v - Verilog source for SPI module Test Bench

Copyright (C) 2007  Steven Yu

This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.

*/

`timescale 1ns/1ns

module spi_master_tb();
reg [1:0] addr;
reg [7:0] in_data;
wire [7:0] out_data;
reg rd;
reg wr;
reg cs;
reg clk;
tri1 miso;
wire mosi;
wire sclk;

spi_master uut(addr, in_data, out_data, rd, wr, cs, clk, miso, mosi, sclk);

integer counter = 0;

initial
begin
    // Init
    addr = 0;
    in_data = 0;
    rd = 0;
    wr = 0;
    cs = 0;
    clk = 0;
    
    #20;
    
    // Set CLK_DIV
    addr = 2;
    in_data = 0;
    wr = 1;
    cs = 1;
    
    #20;
    
    addr = 0;
    in_data = 0;
    wr = 0;
    cs = 0;
    
    #20;
   
   
   // Output from 0 to 255
for(counter = 0; counter < 256; counter = counter + 1)
begin    
    addr = 0;
    in_data = counter;
    wr = 1;
    cs = 1;
    
    #20;
    
    addr = 0;
    in_data = 0;
    wr = 0;
    cs = 0;
    
    #20;
    
    // Poll Busy signal
    addr = 1;
    cs = 1;
    rd = 1;
    #20;
    while(out_data[0] == 1'b1)
    begin
      #20;
    end
    cs = 0;
    rd = 0;
    #20;
end

$stop;

end

// Match Xport 2.0 50 MHz clock on FPGA (20ns period)
always begin clk = ~clk; #10; end

endmodule