代码搜索：out_data
找到约 581 项符合「out_data」的源代码
代码结果 581
www.eeworm.com/read/372591/9502268
c lcd.c
#define LCD_C 1
#include
#include "lcd.h"
#include "chartable.h"
unsigned char gb_ucDegree;
const char ST7637DN_Initial_Table[] =
{
0x01,0x01,
0x02,0
www.eeworm.com/read/164912/10082300
h lms_predict.h
void mcbsp0_init(void);
int mcbsp0_read(void);
void mcbsp0_write(int out_data);
interrupt void mcbsp0_rx_intr(void);
void init_adpf(void);
float adpf(float x, float d);
void init_d
www.eeworm.com/read/355654/10251388
vhd i8051_xrm.vhd
--
-- Copyright (c) 1999-2000 Tony Givargis. Permission to copy is granted
-- provided that this header remains intact. This software is provided
-- with no warranties.
--
-- Version : 2.8
--
-----
www.eeworm.com/read/423217/10579069
bak test2.v.bak
//test in two different clk with transmitter2 and receiver2
module testbench2();
reg Clk1,Clk2,Reset;
wire BitWire;
reg [3:0] ClkCounter1;
reg [3:0] ClkCounter2;
reg in_DataEnable;
reg [7:0] in_D
www.eeworm.com/read/423217/10579079
bak test.v.bak
module testbench1();
reg Clk,Reset;
wire BitWire;
reg [3:0] ClkCounter;
reg in_DataEnable;
reg [7:0] in_Data;
wire [7:0] out_Data;
//connect transmitter and receiver
transmitter DUT1(.in_clk(Cl
www.eeworm.com/read/423217/10579081
v test2.v
//test in two different clk with transmitter2 and receiver2
module testbench2();
reg Clk1,Clk2,Reset;
wire BitWire;
reg [3:0] ClkCounter1;
reg [3:0] ClkCounter2;
reg in_DataEnable;
reg [7:0] in_D
www.eeworm.com/read/423217/10579085
v test.v
//test in the same clk
module testbench1();
reg Clk,Reset;
wire BitWire;
reg [3:0] ClkCounter;
reg in_DataEnable;
reg [7:0] in_Data;
wire [7:0] out_Data;
//connect transmitter and receiver
transm
www.eeworm.com/read/271194/11004506
java marks.java
import java.awt.*;
import java.io.*;
import java.awt.event.*;
public class Marks
{
public static void main(String args[])
{
Frame_FileDialog20_13 f=new Frame_FileDialog20_13();
f.pack();
www.eeworm.com/read/447737/7546017
vhd top.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY timer IS
PORT(
CLK1HZ : IN STD_LOGIC;
SET : IN
www.eeworm.com/read/447737/7546022
vhd timer.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY timer IS
PORT(
CLK1HZ : IN STD_LOGIC;
SET : IN