timer.vhd

多功能计时器,具有校准

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY timer IS
   PORT(
        CLK1HZ : IN        STD_LOGIC;
        SET    : IN        STD_LOGIC;
        MODE   : IN        STD_LOGIC;
        LED1   : OUT       STD_LOGIC_VECTOR(6 DOWNTO 0);
        LED2   : OUT       STD_LOGIC_VECTOR(6 DOWNTO 0);
        LED3   : OUT       STD_LOGIC_VECTOR(6 DOWNTO 0);
        LED4   : OUT       STD_LOGIC_VECTOR(6 DOWNTO 0);
        LED5   : OUT       STD_LOGIC_VECTOR(6 DOWNTO 0);
        LED6   : OUT       STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END timer;
ARCHITECTURE rtl of timer IS
COMPONENT adjuster
    PORT(
         CLK1HZ : IN        STD_LOGIC;
         SET    : IN        STD_LOGIC;
        MODE   : IN        STD_LOGIC;
        EN      : IN       STD_LOGIC;
         S_ENOUT : IN      STD_LOGIC;
        M_ENOUT  : IN      STD_LOGIC;
        CLK      : OUT     STD_LOGIC;
        S_CE     : OUT     STD_LOGIC;
        M_CE     :OUT      STD_LOGIC;
        H_CE     : OUT     STD_LOGIC
);
END COMPONENT;

COMPONENT counter60
PORT(
     CLK1HZ : IN        STD_LOGIC;
     EN      : IN       STD_LOGIC;
     ENOUT   : OUT      STD_LOGIC;
     LOW     : OUT      STD_LOGIC_VECTOR(3 DOWNTO 0);
     HIGH    : OUT      STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;

COMPONENT counter24
PORT(
     CLK1HZ : IN        STD_LOGIC;
     EN      : IN       STD_LOGIC;
     LOW     : OUT      STD_LOGIC_VECTOR(3 DOWNTO 0);
     HIGH    : OUT      STD_LOGIC_VECTOR(3 DOWNTO 0)       
);
END COMPONENT;

COMPONENT display
      PORT(
           in_data    :IN    STD_LOGIC_VECTOR(3 DOWNTO 0);
           out_data   :OUT   STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;

CONSTANT VCC   :STD_LOGIC:='1';
SIGNAL   VCC_CON :STD_LOGIC;
SIGNAL   S_ENOUT :STD_LOGIC;
SIGNAL   M_ENOUT :STD_LOGIC;
SIGNAL   CLK     :STD_LOGIC;
SIGNAL   S_CE :STD_LOGIC;
SIGNAL   M_CE :STD_LOGIC;
SIGNAL   H_CE :STD_LOGIC;
SIGNAL   SL : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL   SH : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL   ML : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL   MH : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL   HL : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL   HH : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN 
    ADJUST_CONTROL: adjuster
    PORT MAP(

CLK1HZ=>CLK1HZ,
SET=>SET,
MODE=>MODE,
EN=>VCC_CON,
S_ENOUT=>S_ENOUT,
M_ENOUT=>M_ENOUT,
CLK=>CLK,
S_CE=>S_CE,
M_CE=>M_CE,
H_CE=>H_CE
);

VCC_CON<=VCC;

SEC_CONTROL:counter60
PORT MAP(
       CLK1HZ=>CLK,
       EN=>S_CE,
       ENOUT=>S_ENOUT,
       LOW=>SL,
       HIGH=>SH
);

MIN_CONTROL:counter60
PORT MAP(
       CLK1HZ=>CLK,
       EN=>M_CE,
       ENOUT=>M_ENOUT,
       LOW=>ML,
       HIGH=>MH
);

HOUR_CONTROL:counter24
PORT MAP(
       CLK1HZ=>CLK,
       EN=>H_CE,
       
       LOW=>HL,
       HIGH=>HH
);

DIS_LED1:display
PORT MAP(
in_data=>SL,
out_data=>LED1
);

DIS_LED2:display
PORT MAP(
in_data=>SH,
out_data=>LED2
);

DIS_LED3:display
PORT MAP(
in_data=>ML,
out_data=>LED3
);

DIS_LED4:display
PORT MAP(
in_data=>MH,
out_data=>LED4
);

DIS_LED5:display
PORT MAP(
in_data=>HL,
out_data=>LED5
);

DIS_LED6:display
PORT MAP(
in_data=>HH,
out_data=>LED6
);

END rtl;