test.v.bak

简单的uart状态机的编写

module testbench1();
    
reg Clk,Reset;
wire BitWire;
reg [3:0] ClkCounter;
reg in_DataEnable;
reg [7:0] in_Data;
wire [7:0] out_Data;

//connect transmitter and receiver
transmitter DUT1(.in_clk(Clk),
                 .in_resetn(Reset),
                 .in_Data(in_Data),
                 .in_DataEnable(in_DataEnable),
                 .out_NextData(NextData),
                 .out_Bit(BitWire)
                 );
receiver DUT2(.in_clk(Clk),
              .in_resetn(Reset),
              .in_bit(BitWire),
              .out_Data(out_Data),
              .out_DataEnable(out_DataEnable),
              .out_ParityError(out_ParityError),
              .out_FrameError(out_FrameErrror)
              );

initial
   begin
     $dumpfile("uart.vcd");
     $dumpvars;
     $dumpon;
     Clk = 1'b0;
     Reset = 1'b0;
     #100 Reset=1'b1;
   end


always #9           
   Clk <= !Clk;
   
always @(posedge Clk or negedge Reset)
   if(!Reset)
      ClkCounter <= 0;
   else
      ClkCounter <= ClkCounter + 1;
      


always @(posedge Clk or negedge Reset )
 if(!Reset)
      begin
      in_Data=8'b0;
      in_DataEnable =1'b0;
      end
   else
   begin
   if((NextData) & (ClkCounter == 0))
     begin
     in_Data=$random;
     in_DataEnable =1'b1;
     $display("Issue data %h", in_Data);
     end
   else
     begin
     //in_Data=8'b0;
     in_DataEnable =1'b0;
     end
   end
   
   
always @(posedge out_DataEnable)
if(out_DataEnable) 
  begin
     if(out_ParityError)
        $display("Parity Error");
     else if (out_FrameErrror)
        $display("Frame Error");
     else
        $display("Receiver data %h", out_Data);
  end

endmodule