代码搜索：out_data
找到约 581 项符合「out_data」的源代码
代码结果 581
www.eeworm.com/read/483608/6599568
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/481648/6636842
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/480938/6654023
h median_33.h
/* ------------------------------------------------------------------------ */
/* 2006.02 for DSP training lab */
/* ==============================================
www.eeworm.com/read/479927/6683674
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/408950/11364321
v iic_master_tb.v
/*
I2C_Master_tb.v - Verilog source for I2C module Test Bench
Copyright (C) 2007 Steven Yu
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Genera
www.eeworm.com/read/406252/11445760
v select.v
module select(data1,data2,data3,data4,data5,data6,data7,data8,sel,out_data);
input[3:0] data1,data2,data3,data4,data5,data6,data7,data8;
input[7:0] sel;
output[3:0] out_data;
reg[3:0] out_data;
www.eeworm.com/read/401363/11558587
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/157170/11735185
h img_pix_expand.h
/* ======================================================================== */
/* TEXAS INSTRUMENTS, INC. */
/*
www.eeworm.com/read/258608/11850606
txt 例八.txt
import java.io.*;
public class Example
{
public static void main(String args[])
{
try
{ FileOutputStream fos=new FileOutputStream("jerry.dat");
DataOutputS
www.eeworm.com/read/344792/11859945
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data