iic_master_tb.v

IIC总线的Master代码

/*

I2C_Master_tb.v - Verilog source for I2C module Test Bench

Copyright (C) 2007  Steven Yu

This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.

*/

`timescale 1ns/1ns

module i2c_master_tb();

reg  [2:0] addr;
reg  [7:0] in_data;
wire [7:0] out_data;
tri1       sda;
tri1       scl;
reg        cs;
reg        rd;
reg        wr;
reg        clk;
wire			iic_busy;

i2c_master uut(.addr(addr), .in_data(in_data), .out_data(out_data), .sda(sda), .scl(scl), .cs(cs), .rd(rd), .wr(wr), .clk(clk), .iic_busy(iic_busy));



task start;
	begin

	addr = 0;
   in_data = 1;
   cs = 1;
   wr = 1;
   #20;
   
   in_data = 0;
   cs = 0;
   wr = 0;
   #20;
	end
endtask

task speed;
begin
 addr = 4;
   in_data = 1;
   cs = 1;
   wr = 1;
   #20;
   
   cs = 0;
   wr = 0;
   #20;
end
endtask

task wait_iic_free;
begin
 addr = 4;
   cs = 1;
   rd = 1;
   #20;
   while(out_data[0] == 1'b1)
   begin
      #20;
   end
   cs = 0;
   rd = 0;
   #20;
end
endtask


initial
begin
   // INIT
   addr = 0;
   in_data = 0;
   cs = 0;
   rd = 0;
   wr = 0;
   clk = 0;
   #20;


   // SPEED (set to 400Kbps)
  

//  start;
//  speed;
//  wait_iic_free;

//  
   // START
  /* addr = 0;
   in_data = 1;
   cs = 1;
   wr = 1;
   #20;
   
   in_data = 0;
   cs = 0;
   wr = 0;
   #20;*/

   // Poll Busy signal to see when I2C module is free
  


   // DATA (Address + Write bit)
 /*  addr = 3;
   in_data = 8'b11110000;
   cs = 1;
   wr = 1;
   #20;

   cs = 0;
   wr = 0;
   #20;
   
   // Poll Busy signal to see when I2C module is free
   addr = 4;
   cs = 1;
   rd = 1;
   #20;
   while(out_data[0] == 1'b1)
   begin
      #20;
   end
   cs = 0;
   rd = 0;
   #20;
    
   
   // WRITE
   addr = 3;
   in_data = 8'b10101010;
   cs = 1;
   wr = 1;
   #20;
   
   cs = 0;
   wr = 0;
   #20;

   // Poll Busy signal to see when I2C module is free
   addr = 4;
   cs = 1;
   rd = 1;
   #20;
   while(out_data[0] == 1'b1)
   begin
      #20;
   end
   cs = 0;
   rd = 0;
   #20;
      
   
   // Test Restart
   addr = 0;
   in_data = 1;
   cs = 1;
   wr = 1;
   #20;
   
   in_data = 0;
   cs = 0;
   wr = 0;
   #20;

   // Poll Busy signal to see when I2C module is free
   addr = 4;
   cs = 1;
   rd = 1;
   #20;
   while(out_data[0] == 1'b1)
   begin
      #20;
   end
   cs = 0;
   rd = 0;
   #20;


   // DATA (Address + Read bit)
   addr = 3;
   in_data = 8'b00001111;
   cs = 1;
   wr = 1;
   #20;

   cs = 0;
   wr = 0;
   #20;

   // Poll Busy signal to see when I2C module is free
   addr = 4;
   cs = 1;
   rd = 1;
   #20;
   while(out_data[0] == 1'b1)
   begin
      #20;
   end
   cs = 0;
   rd = 0;
   #20;
    
   
   // READ
   addr = 2;
   in_data = 1;
   cs = 1;
   wr = 1;
   #20;
   
   cs = 0;
   wr = 0;
   #20;

   // Poll Busy signal to see when I2C module is free
   addr = 4;
   cs = 1;
   rd = 1;
   #20;
   while(out_data[0] == 1'b1)
   begin
      #20;
   end
   cs = 0;
   rd = 0;
   #20;
   
   
   // STOP
   addr = 1;
   in_data = 1;
   cs = 1;
   wr = 1;
   #20;
   
   in_data = 0;
   cs = 0;
   wr = 0;  
   #20;

   // Poll Busy signal to see when I2C module is free
   addr = 4;
   cs = 1;
   rd = 1;
   #20;
   while(out_data[0] == 1'b1)
   begin
      #20;
   end
   cs = 0;
   rd = 0;
   #20;*/
   
   #100000;
   $stop;
end

// Match Xport 2.0 50 MHz clock on FPGA (20ns period)
always begin #10; clk = ~clk; end

endmodule