代码搜索：mult
找到约 6,230 项符合「mult」的源代码
代码结果 6,230
www.eeworm.com/read/420062/10820385
h mult.h
//////////////////////////////////////////////////////////////////
// Mult18X18 example.
//
// Copyright(c) 2003-2005 Impulse Accelerated Technologies, Inc.
//
#define INPUT_FILE "operands_in
www.eeworm.com/read/275330/10823369
exe mult.exe
www.eeworm.com/read/419081/10886688
dat _mult.dat
0
0.015864
0.031712
0.047528
0.0632962
0.0790007
0.0946256
0.110155
0.125574
0.140866
0.156017
0.17101
0.185831
0.200465
0.214897
0.229113
0.243098
0.256839
0.27032
0.28353
0.29645
www.eeworm.com/read/419081/10886771
dat _mult.dat
0
0.015864
0.031712
0.047528
0.0632962
0.0790007
0.0946256
0.110155
0.125574
0.140866
0.156017
0.17101
0.185831
0.200465
0.214897
0.229113
0.243098
0.256839
0.27032
0.28353
0.29645
www.eeworm.com/read/419004/10889768
v mult.v
module mult(outcome,a,b);
parameter size=8;
input[size:1] a,b;
output[2*size:1] outcome;
assign outcome=a*b;
endmodule
www.eeworm.com/read/466825/7021068
vhd mult.vhd
-- MULTIPLEXER TO CHOOSE BETWEEN CLOCK AND C0
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;
entity mul
www.eeworm.com/read/466829/7021110
vhd mult.vhd
-- MULTIPLEXER TO CHOOSE BETWEEN CLOCK AND C0
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;
entity mul
www.eeworm.com/read/465744/7044725
bsf mult.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/465744/7044729
vwf mult.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/465744/7044735
vhd mult.vhd
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mult is
port(
clk,rst: in std_logic;
xa,xb: i