mult.vhd

来自「采用加法树流水线乘法构造八位乘法器」· VHDL 代码 · 共 56 行

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity mult is 
	port(
		clk,rst:	             in std_logic;
		xa,xb:		             in std_logic_vector(7 downto 0);
		p0,p1,p2,p3,p4,p5,p6,p7: out std_logic_vector(7 downto 0));
end entity mult;

architecture behave of mult is
	signal reg1:	std_logic_vector(23 downto 0);
	signal reg2:	std_logic_vector(22 downto 0);


begin
	process(clk,rst)
	variable i:integer;
		begin
		i:=0;
		for i in 0 to 7  loop
		p0(i)<=xa(i) and xb(0);
		end loop;
		i:=0;
		for i in 0 to 7  loop
		p1(i)<=xa(i) and xb(1);
		end loop;
		i:=0;
		for i in 0 to 7  loop
		p2(i)<=xa(i) and xb(2);
		end loop;
		i:=0;
		for i in 0 to 7  loop
		p3(i)<=xa(i) and xb(3);
		end loop;
		i:=0;
		for i in 0 to 7  loop
		p4(i)<=xa(i) and xb(4);
		end loop;
		i:=0;
		for i in 0 to 7  loop
		p5(i)<=xa(i) and xb(5);
		end loop;
		i:=0;
		for i in 0 to 7  loop
		p6(i)<=xa(i) and xb(6);
		end loop;	
		i:=0;
		for i in 0 to 7  loop
		p7(i)<=xa(i) and xb(7);
		end loop;
	end process ;
end behave;