代码搜索：modelSim
找到约 1,834 项符合「modelSim」的源代码
代码结果 1,834
www.eeworm.com/read/364724/9897073
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# Reading C:/Modeltech_6.1e/tcl/vsim/pref.tcl
# do clk_test_v.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.1e Compiler 2006.03 Mar 8 2006
www.eeworm.com/read/364723/9897135
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# Reading C:/Modeltech_6.1f/tcl/vsim/pref.tcl
# // ModelSim SE 6.1f May 12 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WO
www.eeworm.com/read/420737/10778333
gfl clk.gfl
# Bencher : Creating project file
test_tb_bencher.prj
# ProjNav -> New Source -> TBW
test_tb.vhw
test_tb.ano
test_tb.tfw
test_tb.ant
# Bencher : Creating project file
clk_tb_bencher.prj
# Pro
www.eeworm.com/read/462646/7198806
vhdsim_synth filtro_fir_mac.vhdsim_synth
filtro_fir_mac.vhdsim_synth -- generated only for ProjNav status tracking
Simulation Model Target: ModelSim SE (VHDL)
www.eeworm.com/read/462646/7198880
vhdsim_par filtro_fir_mac.vhdsim_par
filtro_fir_mac.vhdsim_par -- generated only for ProjNav status tracking
Simulation Model Target: ModelSim SE (VHDL)
www.eeworm.com/read/320300/13428721
mti nand_interface.cr.mti
nand_flash_testbench.v {1 {vlog -work work nand_flash_testbench.v
Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
-- Compiling module nand_flash_testbench
Top level module
www.eeworm.com/read/488475/6487579
sft part4.sft
set tool_name "ModelSim (Verilog)"
set corner_file_list {
{{"Slow Model"} {part4.vo part4_v.sdo}}
}
www.eeworm.com/read/488475/6487688
sft part6.sft
set tool_name "ModelSim (Verilog)"
set corner_file_list {
{{"Slow Model"} {part6.vo part6_v.sdo}}
}
www.eeworm.com/read/488475/6487835
sft part1.sft
set tool_name "ModelSim (Verilog)"
set corner_file_list {
{{"Slow Model"} {part1.vo part1_v.sdo}}
}
www.eeworm.com/read/477557/6738568
vhdsim_par key_number_encoder.vhdsim_par
key_number_encoder.vhdsim_par -- generated only for ProjNav status tracking
Simulation Model Target: ModelSim SE (VHDL)