clk.gfl

通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。

# Bencher : Creating project file
test_tb_bencher.prj
# ProjNav -> New Source -> TBW
test_tb.vhw
test_tb.ano
test_tb.tfw
test_tb.ant
# Bencher : Creating project file
clk_tb_bencher.prj
# ProjNav -> New Source -> TBW
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# Bencher : Creating project file
clk_tb_bencher.prj
# ProjNav -> New Source -> TBW
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher : Creating project file
clk_tb_bencher.prj
# ProjNav -> New Source -> TBW
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher : Creating project file
clk_tb_bencher.prj
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# xst flow : RunXST
clkdiv_summary.html
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# xst flow : RunXST
clkdiv_summary.html
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
clkdiv.lso
# xst flow : RunXST
clkdiv_summary.html
# xst flow : RunXST
clkdiv.syr
clkdiv.prj
clkdiv.sprj
clkdiv.ana
clkdiv.stx
clkdiv.cmd_log
clkdiv.ngr
# View RTL Schematic
clkdiv.ngr
clkdiv.ngc
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# xst flow : RunXST
clkdiv_summary.html
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
clk_tb_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_tb.vhw
clk_tb.ano
clk_tb.tfw
clk_tb.ant
# ModelSim : Simulate Behavioral VHDL Model
clk_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf