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来自「just division the clock into 2」· 代码 · 共 26 行

# Reading C:/Modeltech_6.1e/tcl/vsim/pref.tcl 
# do clk_test_v.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.1e Compiler 2006.03 Mar  8 2006
# -- Compiling module clk
# 
# Top level modules:
# 	clk
# Model Technology ModelSim SE vlog 6.1e Compiler 2006.03 Mar  8 2006
# -- Compiling module clk_test_v
# 
# Top level modules:
# 	clk_test_v
# Model Technology ModelSim SE vlog 6.1e Compiler 2006.03 Mar  8 2006
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps clk_test_v glbl 
# Loading work.clk_test_v
# Loading work.clk
# Loading work.glbl
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs