代码搜索：modelSim

找到约 1,834 项符合「modelSim」的源代码

代码结果 1,834
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/374512/9401388

vhdsim_synth clock.vhdsim_synth

CLOCK.vhdsim_synth -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (VHDL)
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www.eeworm.com/read/371229/9561081

sh build_float_vpi.sh

# This constructs a DLL plug in for Modelsim from float_vpi.cpp # It contains a few floating point helper functions. # The Modelim PLI interface library - modify Modelsim path if necessary if [ -
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www.eeworm.com/read/174927/9568309

gfl dpram2.gfl

# XST (Creating Lso File) : dpram2.lso # xst flow : RunXST dpram2.syr dpram2.prj dpram2.sprj dpram2.ana dpram2.stx dpram2.cmd_log dpram2.ngc dpram2.ngr # Implmentation : Translate __projn
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www.eeworm.com/read/360252/10105616

gfl bianmaqi.gfl

# XST (Creating Lso File) : bianma.lso # xst flow : RunXST bianma.syr bianma.prj bianma.sprj bianma.ana bianma.stx bianma.cmd_log bianma.ngr # View RTL Schematic bianma.ngr bianma.ngc #
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www.eeworm.com/read/359174/10162778

versim_par serial.versim_par

serial.versim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (Verilog)
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www.eeworm.com/read/359174/10162883

versim_par icx229.versim_par

ICX229.versim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (Verilog)
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www.eeworm.com/read/359174/10162967

versim_map shuju.versim_map

shuju.versim_map -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (Verilog)
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www.eeworm.com/read/359174/10162978

versim_par clk.versim_par

clk.versim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (Verilog)
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www.eeworm.com/read/359174/10163029

versim_par shuju.versim_par

shuju.versim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (Verilog)
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www.eeworm.com/read/359174/10163052

gfl icx229al.gfl

# xst flow : RunXST ICX229_summary.html ProjNav -> New -> Test Fixture __projnav/createTF.err # ModelSim : Simulate Behavioral Verilog Model test_v.fdo # ModelSim : Simulate Behavioral Verilog M
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