icx229al.gfl

SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序

# xst flow : RunXST
ICX229_summary.html
ProjNav -> New -> Test Fixture
__projnav/createTF.err
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
ICX229_summary.html
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
ICX229_summary.html
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
ICX229_summary.html
ProjNav -> New -> Test Fixture
__projnav/createTF.err
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test1_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
ProjNav -> New -> Test Fixture
__projnav/createTF.err
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
ICX229_summary.html
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
ICX229_summary.html
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
ICX229_summary.html
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
ICX229_summary.html
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngr
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngr
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngr
# XST (Creating Lso File) : 
ICX229.lso
# xst flow : RunXST
ICX229_summary.html
# xst flow : RunXST
ICX229.syr
ICX229.prj
ICX229.sprj
ICX229.ana
ICX229.stx
ICX229.cmd_log
ICX229.ngc
ICX229.ngr
# XST (Creating Lso File) : 
ICX229.lso
# xst flow : RunXST
ICX229_summary.html
# xst flow : RunXST
ICX229.syr
ICX229.prj
ICX229.sprj
ICX229.ana
ICX229.stx
ICX229.cmd_log
ICX229.ngc
ICX229.ngr
# XST (Creating Lso File) : 
VSP2232.lso
# xst flow : RunXST
VSP2232_summary.html
# xst flow : RunXST
VSP2232.syr
VSP2232.prj
VSP2232.sprj
VSP2232.ana
VSP2232.stx
VSP2232.cmd_log
VSP2232.ngc
VSP2232.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngc
serial.ngr
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngc
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngc
serial.ngr
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
ProjNav -> New -> Test Fixture
__projnav/createTF.err
# ModelSim : Simulate Behavioral Verilog Model
test3_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test3_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
clk.lso
# xst flow : RunXST
clk_summary.html
# xst flow : RunXST
clk.syr
clk.prj
clk.sprj
clk.ana
clk.stx
clk.cmd_log
clk.ngc
clk.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\test\icx229al/_ngo"
clk.ngd
clk_ngdbuild.nav
clk.bld
.untf
clk.cmd_log
# Implementation : Map
clk_summary.html
# Implementation : Map
clk_map.ncd
clk.ngm
clk.pcf
clk.nc1
clk.mrp
clk_map.mrp
clk.mdf
clk.cmd_log
MAP_NO_GUIDE_FILE_CPF "clk"
clk_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
clk.twr
clk.twx
clk.tsi
clk.cmd_log
# Implementation : Place & Route
clk_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
clk.ncd
clk.par
clk.pad
clk_pad.txt
clk_pad.csv
clk.pad_txt
clk.dly
reportgen.log
clk.xpi
clk.grf
clk.itr
clk_last_par.ncd
clk.placed_ncd_tracker
clk.routed_ncd_tracker
clk.cmd_log
PAR_NO_GUIDE_FILE_CPF "clk"
# Implementation : Generate Post-Place & Route Simulation Model
clk_timesim.v
clk_timesim.nlf
clk.versim_par
clk.par_nlf
clk.cmd_log
clk_timesim.v
clk_timesim.sdf
clk_timesim.sdf
# ModelSim : Simulate Post-Place & Route VHDL Model
test3_v.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
ICX229_summary.html
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
ICX229_summary.html
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
ICX229_summary.html
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Verilog : Create Schematic Symbol
data.spl
__projnav/jhdparse.log
# Verilog : Create Schematic Symbol
ICX229.spl
__projnav/jhdparse.log
# Verilog : Create Schematic Symbol
serial.spl
__projnav/jhdparse.log
# Verilog : Create Schematic Symbol
VSP2232.spl
__projnav/jhdparse.log
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Project -> New Source -> Architecture Wizard
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# XAW : Create Schematic Symbol
clk4.spl
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
ProjNav -> New -> Test Fixture
__projnav/createTF.err
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model