icx229al.gfl

来自「SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序」· GFL 代码 · 共 3,174 行 · 第 1/5 页

top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
top.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\test\icx229al/_ngo"
top.ngd
top_ngdbuild.nav
top.bld
.untf
top.cmd_log
# Implementation : Map
top_summary.html
# Implementation : Map
top_map.ncd
top.ngm
top.pcf
top.nc1
top.mrp
top_map.mrp
top.mdf
top.cmd_log
MAP_NO_GUIDE_FILE_CPF "top"
top_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
top.twr
top.twx
top.tsi
top.cmd_log
# Implementation : Place & Route
top_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top_pad.txt
top_pad.csv
top.pad_txt
top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Implementation : Generate Post-Place & Route Simulation Model
top_timesim.v
top_timesim.nlf
top.versim_par
top.par_nlf
top.cmd_log
top_timesim.v
top_timesim.sdf
top_timesim.sdf
# ModelSim : Simulate Post-Place & Route VHDL Model
top_top_sch_tb.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
top_top_sch_tb.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# View RTL Schematic
ICX229.ngr
ICX229.ngc
# View RTL Schematic
top.ngr
top.ngc
# XST (Creating Lso File) : 
shuju.lso
# xst flow : RunXST
shuju_summary.html
# xst flow : RunXST
shuju.syr
shuju.prj
shuju.sprj
shuju.ana
shuju.stx
shuju.cmd_log
shuju.ngc
shuju.ngr
# Verilog : Create Schematic Symbol
shuju.spl
__projnav/jhdparse.log
# XST (Creating Lso File) : 
VSP2232.lso
# xst flow : RunXST
VSP2232_summary.html
# xst flow : RunXST
VSP2232.syr
VSP2232.prj
VSP2232.sprj
VSP2232.ana
VSP2232.stx
VSP2232.cmd_log
VSP2232.ngc
VSP2232.ngr
# Verilog : Create Schematic Symbol
VSP2232.spl
__projnav/jhdparse.log
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngc
serial.ngr
# Verilog : Create Schematic Symbol
serial.spl
__projnav/jhdparse.log
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
shuju.ngc
top.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
shuju.ngr
top.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\test\icx229al/_ngo"
top.ngd
top_ngdbuild.nav
top.bld
.untf
top.cmd_log
# Implementation : Map
top_summary.html
# Implementation : Map
top_map.ncd
top.ngm
top.pcf
top.nc1
top.mrp
top_map.mrp
top.mdf
top.cmd_log
MAP_NO_GUIDE_FILE_CPF "top"
top_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
top.twr
top.twx
top.tsi
top.cmd_log
# Implementation : Place & Route
top_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top_pad.txt
top_pad.csv
top.pad_txt
top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Implementation : Generate Post-Place & Route Simulation Model
top_timesim.v
top_timesim.nlf
top.versim_par
top.par_nlf
top.cmd_log
top_timesim.v
top_timesim.sdf
top_timesim.sdf
# ModelSim : Simulate Post-Place & Route VHDL Model
top_top_sch_tb.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
ICX229.lso
# xst flow : RunXST
ICX229_summary.html
# xst flow : RunXST
ICX229.syr
ICX229.prj
ICX229.sprj
ICX229.ana
ICX229.stx
ICX229.cmd_log
ICX229.ngc
ICX229.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\test\icx229al/_ngo"
ICX229.ngd
ICX229_ngdbuild.nav
ICX229.bld
.untf
ICX229.cmd_log
# Implementation : Map
ICX229_summary.html
# Implementation : Map
ICX229_map.ncd
ICX229.ngm
ICX229.pcf
ICX229.nc1
ICX229.mrp
ICX229_map.mrp
ICX229.mdf
ICX229.cmd_log
MAP_NO_GUIDE_FILE_CPF "ICX229"
ICX229_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
ICX229.twr
ICX229.twx
ICX229.tsi
ICX229.cmd_log
# Implementation : Place & Route
ICX229_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
ICX229.ncd
ICX229.par
ICX229.pad
ICX229_pad.txt
ICX229_pad.csv
ICX229.pad_txt
ICX229.dly
reportgen.log
ICX229.xpi
ICX229.grf
ICX229.itr
ICX229_last_par.ncd
ICX229.placed_ncd_tracker
ICX229.routed_ncd_tracker
ICX229.cmd_log
PAR_NO_GUIDE_FILE_CPF "ICX229"
# Implementation : Generate Post-Place & Route Simulation Model
ICX229_timesim.v
ICX229_timesim.nlf
ICX229.versim_par
ICX229.par_nlf
ICX229.cmd_log
ICX229_timesim.v
ICX229_timesim.sdf
ICX229_timesim.sdf
# ModelSim : Simulate Post-Place & Route VHDL Model
test_v.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# xst flow : RunXST
top_summary.html
# ModelSim : Simulate Behavioral Verilog Model
test_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngc
serial.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\test\icx229al/_ngo"
serial.ngd
serial_ngdbuild.nav
serial.bld
.untf
serial.cmd_log
# Implementation : Map
serial_summary.html
# Implementation : Map
serial_map.ncd
serial.ngm
serial.pcf
serial.nc1
serial.mrp
serial_map.mrp
serial.mdf
serial.cmd_log
MAP_NO_GUIDE_FILE_CPF "serial"
serial_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
serial.twr
serial.twx
serial.tsi
serial.cmd_log
# Implementation : Place & Route
serial_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
serial.ncd
serial.par
serial.pad
serial_pad.txt
serial_pad.csv
serial.pad_txt
serial.dly
reportgen.log
serial.xpi
serial.grf
serial.itr
serial_last_par.ncd
serial.placed_ncd_tracker
serial.routed_ncd_tracker
serial.cmd_log
PAR_NO_GUIDE_FILE_CPF "serial"
# Implementation : Generate Post-Place & Route Simulation Model
serial_timesim.v
serial_timesim.nlf
serial.versim_par
serial.par_nlf
serial.cmd_log
serial_timesim.v
serial_timesim.sdf
serial_timesim.sdf
# ModelSim : Simulate Post-Place & Route VHDL Model
test2_v.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
VSP2232.lso
# xst flow : RunXST
VSP2232_summary.html
# xst flow : RunXST
VSP2232.syr
VSP2232.prj
VSP2232.sprj
VSP2232.ana
VSP2232.stx
VSP2232.cmd_log
VSP2232.ngc
VSP2232.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\test\icx229al/_ngo"
VSP2232.ngd
VSP2232_ngdbuild.nav
VSP2232.bld
.untf
VSP2232.cmd_log
# Implementation : Map
VSP2232_summary.html
# Implementation : Map
VSP2232_map.ncd
VSP2232.ngm
VSP2232.pcf
VSP2232.nc1
VSP2232.mrp
VSP2232_map.mrp
VSP2232.mdf
VSP2232.cmd_log
MAP_NO_GUIDE_FILE_CPF "VSP2232"
VSP2232_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
VSP2232.twr
VSP2232.twx
VSP2232.tsi
VSP2232.cmd_log
# Implementation : Place & Route
VSP2232_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
VSP2232.ncd
VSP2232.par
VSP2232.pad
VSP2232_pad.txt
VSP2232_pad.csv
VSP2232.pad_txt
VSP2232.dly
reportgen.log
VSP2232.xpi
VSP2232.grf
VSP2232.itr
VSP2232_last_par.ncd
VSP2232.placed_ncd_tracker
VSP2232.routed_ncd_tracker
VSP2232.cmd_log
PAR_NO_GUIDE_FILE_CPF "VSP2232"
# Implementation : Generate Post-Place & Route Simulation Model
VSP2232_timesim.v
VSP2232_timesim.nlf
VSP2232.versim_par
VSP2232.par_nlf
VSP2232.cmd_log
VSP2232_timesim.v
VSP2232_timesim.sdf
VSP2232_timesim.sdf
# ModelSim : Simulate Post-Place & Route VHDL Model
test1_v.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
ProjNav -> New -> Test Fixture
__projnav/createTF.err
# XST (Creating Lso File) : 
shuju.lso
# xst flow : RunXST
shuju_summary.html
# xst flow : RunXST
shuju.syr
shuju.prj
shuju.sprj
shuju.ana
shuju.stx
shuju.cmd_log
shuju.ngc
shuju.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\test\icx229al/_ngo"
shuju.ngd
shuju_ngdbuild.nav
shuju.bld
.untf
shuju.cmd_log
# Implementation : Map
shuju_summary.html
# Implementation : Map
shuju_map.ncd
shuju.ngm
shuju.pcf
shuju.nc1
shuju.mrp
shuju_map.mrp
shuju.mdf
shuju.cmd_log
MAP_NO_GUIDE_FILE_CPF "shuju"
shuju_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
shuju.twr
shuju.twx
shuju.tsi
shuju.cmd_log
# Implementation : Place & Route
shuju_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
shuju.ncd
shuju.par
shuju.pad
shuju_pad.txt
shuju_pad.csv
shuju.pad_txt
shuju.dly
reportgen.log
shuju.xpi
shuju.grf
shuju.itr
shuju_last_par.ncd
shuju.placed_ncd_tracker
shuju.routed_ncd_tracker
shuju.cmd_log
PAR_NO_GUIDE_FILE_CPF "shuju"
# Implementation : Generate Post-Place & Route Simulation Model
shuju_timesim.v
shuju_timesim.nlf
shuju.versim_par
shuju.par_nlf
shuju.cmd_log
shuju_timesim.v
shuju_timesim.sdf
shuju_timesim.sdf
# ModelSim : Simulate Post-Place & Route VHDL Model
test3_v.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
test3_v.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test3_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
ICX229.lso
# xst flow : RunXST
ICX229_summary.html
# xst flow : RunXST
ICX229.syr
ICX229.prj
ICX229.sprj
ICX229.ana
ICX229.stx
ICX229.cmd_log
ICX229.ngc
ICX229.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\test\icx229al/_ngo"
ICX229.ngd
ICX229_ngdbuild.nav
ICX229.bld
.untf
ICX229.cmd_log
# Implementation : Map
ICX229_summary.html
# Implementation : Map
ICX229_map.ncd
ICX229.ngm
ICX229.pcf
ICX229.nc1
ICX229.mrp
ICX229_map.mrp
ICX229.mdf
ICX229.cmd_log
MAP_NO_GUIDE_FILE_CPF "ICX229"
ICX229_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
ICX229.twr
ICX229.twx
ICX229.tsi
ICX229.cmd_log
# Implementation : Place & Route
ICX229_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
ICX229.ncd
ICX229.par
ICX229.pad
ICX229_pad.txt
ICX229_pad.csv
ICX229.pad_txt
ICX229.dly
reportgen.log
ICX229.xpi
ICX229.grf
ICX229.itr
ICX229_last_par.ncd
ICX229.placed_ncd_tracker
ICX229.routed_ncd_tracker
ICX229.cmd_log
PAR_NO_GUIDE_FILE_CPF "ICX229"
# Implementation : Generate Post-Place & Route Simulation Model
ICX229_timesim.v
ICX229_timesim.nlf
ICX229.versim_par
ICX229.par_nlf
ICX229.cmd_log
ICX229_timesim.v
ICX229_timesim.sdf
ICX229_timesim.sdf
# ModelSim : Simulate Post-Place & Route VHDL Model
test_v.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top_summary.html
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
shuju.ngc
top.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
shuju.ngr
top.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp