代码搜索：modelSim
找到约 1,834 项符合「modelSim」的源代码
代码结果 1,834
www.eeworm.com/read/271060/11010311
do comp_io.do
#
# ModelSim Compiler 'DO'
#
# Build the Programable I/O port model
vcom -93 -work WORK {../ioport/ioport.vhd}
# Build the Wishbone wrapper
vcom -93 -work WORK {../ioport/wb_ioport.vhd}
www.eeworm.com/read/297703/8002951
_info
m255
13
cModel Technology
dC:\Documents and Settings\zhentizhi\桌面\modelsim 资料\source\chap3
www.eeworm.com/read/139799/13130425
txt readme.txt
目录内容:
\chap-02 ～ chap-18 本书相应章节实例的VHDL源代码。
__________________________________________________________________
使用方法：
建议用户使用如下仿真器仿真本书中的VHDL源代码：
A.微机用户
如果是微机用户可以使用Aldec的Active-HDL，
由于涉
www.eeworm.com/read/231687/14223304
vcd keypadscan.vcd
$date
Sun Mar 06 19:49:06 2005
$end
$version
ModelSim Version 6.0a
$end
$timescale
1ps
$end
www.eeworm.com/read/394465/8223349
entries
/modelsim.ini/1.1.1.1/Thu Sep 20 16:00:54 2007//
/run/1.1.1.1/Thu Sep 20 16:00:54 2007//
D
www.eeworm.com/read/236280/14023606
transcript
# Reading D:/yuanmodsim/tcl/vsim/pref.tcl
# The checkout of feature vsim-viewer has been disallowed.
# The license came from an uncounted nodelocked license and
# an instance of ModelSim is alread
www.eeworm.com/read/389033/8552209
txt 说明.txt
0.最简单的SystemC程序：hello, world.
1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。
2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。
3.如何在SystemC中实现延时（类似verilog中的#time）的例子。
4.SystemC文档《User Guide》中的例子。
www.eeworm.com/read/286093/8788806
gfl top.gfl
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ProjNav -> New -> Test
www.eeworm.com/read/375761/9350303
gfl aa.gfl
# ProjNav -> New Source -> TBW
d:\xilinxise6.2\aa\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
www.eeworm.com/read/374512/9401138
vhdsim_synth alarm.vhdsim_synth
alarm.vhdsim_synth -- generated only for ProjNav status tracking
Simulation Model Target: ModelSim SE (VHDL)