aa.gfl

xilinx环境下开发vhdl语言串行接口设计

# ProjNav -> New Source -> TBW
d:\xilinxise6.2\aa\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test2.vhw
test2.ano
test2.tfw
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
test2.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test2.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test2.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test2.vhw
test2.ano
test2.tfw
# ModelSim : Generate Expected Simulation Results
test2.ado
test2.ano
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
rev.lso
# xst flow : RunXST
rev.syr
rev.prj
rev.sprj
rev.ana
rev.stx
rev.cmd_log
# XST (Creating Lso File) : 
rev.lso
# xst flow : RunXST
rev.syr
rev.prj
rev.sprj
rev.ana
rev.stx
rev.cmd_log
# XST (Creating Lso File) : 
rev.lso
# xst flow : RunXST
rev.syr
rev.prj
rev.sprj
rev.ana
rev.stx
rev.cmd_log
# XST (Creating Lso File) : 
rev.lso
# xst flow : RunXST
rev.syr
rev.prj
rev.sprj
rev.ana
rev.stx
rev.cmd_log
# XST (Creating Lso File) : 
rev.lso
# xst flow : RunXST
rev.syr
rev.prj
rev.sprj
rev.ana
rev.stx
rev.cmd_log
# XST (Creating Lso File) : 
rev.lso
# xst flow : RunXST
rev.syr
rev.prj
rev.sprj
rev.ana
rev.stx
rev.cmd_log
# XST (Creating Lso File) : 
rev.lso
# xst flow : RunXST
rev.syr
rev.prj
rev.sprj
rev.ana
rev.stx
rev.cmd_log
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
bps.ngc
bps.ngr
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
bps.ngc
bps.ngr
# ProjNav -> New Source -> TBW
E:\aa\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test1.vhw
test1.ano
test1.tfw
# ModelSim : Simulate Behavioral VHDL Model
test1.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test1.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
bps.ngc
bps.ngr
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
bps.ngc
bps.ngr
# ModelSim : Simulate Behavioral VHDL Model
test1.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
bps.ngc
bps.ngr
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
bps.ngc
bps.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test1.vhw
test1.ano
test1.tfw
# ModelSim : Simulate Behavioral VHDL Model
test1.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
bps.ngc
bps.ngr
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
bps.ngc
bps.ngr
# ModelSim : Simulate Behavioral VHDL Model
test1.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test1.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
bps.ngc
bps.ngr
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
bps.ngc
bps.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test1.vhw
test1.ano
test1.tfw
# ModelSim : Simulate Behavioral VHDL Model
test1.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
test2.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# ProjNav -> New Source -> TBW
E:\aa\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test5.vhw
test5.ano
test5.tfw
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test5.vhw
test5.ano
test5.tfw
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log