代码搜索：modelSim
找到约 1,834 项符合「modelSim」的源代码
代码结果 1,834
www.eeworm.com/read/467448/7012966
mti dds.cr.mti
G:/eda/qdds/data_juchi.vhd {0 {vcom -work work -2002 -explicit -novopt G:/eda/qdds/data_juchi.vhd
Model Technology ModelSim SE vcom 6.1f Compiler 2006.05 May 12 2006
-- Loading package standard
--
www.eeworm.com/read/210238/7127412
transcript
# Reading C:/Modeltech_xe/tcl/vsim/pref.tcl
# do bj_Tw.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# --
www.eeworm.com/read/457417/7325742
mti analytic_filter.cr.mti
../vhdl/real_pole_filter_shift_reg.vhd {1 {vcom -work work -2002 -explicit Z:/media/MOBILE2/homepage/content/hilbert_transformer/vhdl/real_pole_filter_shift_reg.vhd
Model Technology ModelSim ALTERA v
www.eeworm.com/read/299125/7886715
mti sin4.cr.mti
E:/AAXIAOLI/boxing/sin4.vhd {1 {vcom -work work -2002 -explicit E:/AAXIAOLI/boxing/sin4.vhd
Model Technology ModelSim SE vcom 6.0c Compiler 2005.02 Feb 2 2005
-- Loading package standard
-- Loadin
www.eeworm.com/read/399140/7886770
do post_sim.do
# 8b/10b Post Route Timing Simulation ModelSim DO file
# Create work library
vlib work
# Compile package files
vcom -just e -93 -explicit -work work pkg_convert.vhd
vcom -skip e -93 -explici
www.eeworm.com/read/399139/7886896
do post_sim.do
# 8b/10b Post Route Timing Simulation ModelSim DO file
# Create work library
vlib work
# Compile package files
vcom -just e -93 -explicit -work work pkg_convert.vhd
vcom -skip e -93 -explici
www.eeworm.com/read/333374/12685482
mti atm.cr.mti
{F:/course/Boradband Network/fpga/sim/atm.vhd} {2 {vcom -work work -2002 -explicit -novopt {F:/course/Boradband Network/fpga/sim/atm.vhd}
Model Technology ModelSim SE vcom 6.1d Compiler 2006.01 Jan 2
www.eeworm.com/read/109657/6173164
do compile_and_run_rtl_fullmodel.do
#
# Verilog Build requirements for RTL simulation of the Full Stripe Model
# Device = epxa10
vlib work
vlog "$env(MG_MODEL_PATH)/epxa10/$env(MG_MODEL_REV)/mti_modelsim_verilog/apex20ke_stripe.
www.eeworm.com/read/109657/6173165
do compile_and_run_timing_fullmodel.do
##
# Verilog Build requirements for Timing simulation of the Full Stripe Model
# Device = epxa10
vlib work
vlog "$env(MG_MODEL_PATH)/epxa10/$env(MG_MODEL_REV)/mti_modelsim_verilog/apex20ke_str
www.eeworm.com/read/109657/6173170
do compile_and_run_rtl_fullmodel.do
#
# Verilog Build requirements for RTL simulation of the Full Stripe Model
# Device = epxa10
vlib work
vlog "$env(MG_MODEL_PATH)/epxa10/$env(MG_MODEL_REV)/mti_modelsim_verilog/apex20ke_stripe.