compile_and_run_rtl_fullmodel.do

altera epxa1开发板的例子程序

#
# Verilog Build requirements for RTL simulation of the Full Stripe Model
#   Device = epxa10

vlib work
vlog "$env(MG_MODEL_PATH)/epxa10/$env(MG_MODEL_REV)/mti_modelsim_verilog/apex20ke_stripe.v"
vlog "$env(MG_MODEL_PATH)/epxa10/$env(MG_MODEL_REV)/mti_modelsim_verilog/alt_exc_stripe.v"

############################################################################################
#
#   This file should be called by the users compile/simulation do file with something like
#   the following near the top,
#
#       do build_rtl_fullmodel_epxa10_v.do
#
#
#   *** For the VHDL build file see `build_rtl_fullmodel_vhd.do' ***
#
#   
#   Module Hierarchy is:     
#                           alt_exc_stripe (The LPM)
#                                |
#                            ---------
#                           |         |
#                        epxa10top   bidir
#                           |
#                       --------
#                      |        |
#                   epxa10    apex_pll
#
#
#
#    `model_wrappers.v' contains modules `epxa10top'      and `apex_pll'
#    `alt_exc_stripe.v' contains modules `alt_exc_stripe' and `bidir'
#
#   Note: epxa10 is a tool/platform dependant file, whereas
#    apex_pll and the levels of hierarchy above are all tool/platform independant.
#
#
#   Note $env(MG_MODEL_PATH) is set to the following (see env_setup.txt),
#
#       $env(QUARTUS_ROOTDIR)/eda/sim_lib/excalibur/stripe_model_<PLATFORM>/ModelGen/models
#
#   where <PLATFORM> = NT | solaris | hpux
#
#
#   $env(MG_MODEL_REV) is set to the following
#
#       r0
#
############################################################################################

#
#   Compile the example design
#
# Compile the test-bench and all the modules below it

vlog ../../stripe.v
vlog ../../arm_top.v
vlog ../../../rtl/pld_dpram.v
vlog ../../../testbench/arm_top_tb.v 

###############################################################################
#
# Notes:
#   The above command line (spread over several lines for clarity by using \ ) means;
#   
#   (1) Compile the file ../../testbench/arm_top_tb.v,
#
#   (2) "+incdir+../../verilog"
#       Look for any include files in ../../verilog
#
#   (3) "-y ../../verilog"
#       Search recursively for any modules required by the top-level
#       (the testbench file in this case) in directory ../../verilog
#       "+libext+.v+"
#       ...and in doing so the modules are to be found in a file
#       of the same name with the extension .v
#
#   This is a good way to do things because you dont have to keep changing
#   this build file every time you change your design hierarchy or filenames.
#
###############################################################################
        
#
#   Run the simulation
#
vsim work.arm_top_tb
do wave_rtl_fullstripe.do
run -all