代码搜索：ispLEVER
找到约 314 项符合「ispLEVER」的源代码
代码结果 314
www.eeworm.com/read/244041/12896462
bl1 addr_select.bl1
#$ TOOL ispLEVER 5.1.02.70.06.06.SP2006.02
#$ DATE Sun Dec 03 17:53:45 2006
#$ MODULE addr_select
#$ PINS 11 a_2_ s_7_ a_1_ a_0_ s_6_ s_5_ s_4_ s_3_ s_2_ s_1_ s_0_
.model addr_select
.inputs a_
www.eeworm.com/read/244041/12896513
log automake.log
ispLEVER Auto-Make Log File
---------------------------
Starting: 'C:\ispTOOLS5_1\ispcpld\bin\checkini.exe -err=automake.err "C:\ispTOOLS5_1\ispcpld\config\gen_GAL.ini"'
Done: completed success
www.eeworm.com/read/260117/11746503
log stdout.log
Using OEM Licensing.
Starting: D:\PROGRAM\ISPLEVER\SYNPBASE\bin\mbin\synplify.exe
Install: D:\PROGRAM\ISPLEVER\SYNPBASE
Date: Tue Jul 17 10:47:41 2007
Version: 8.6.2B
Argu
www.eeworm.com/read/251270/12355067
bl1 3rs.bl1
#$ TOOL ispLEVER 5.0.01.73.31.05_Starter
#$ DATE Mon Aug 14 19:03:34 2006
#$ TITLE 3rs.bls
#$ MODULE 3rs
#$ PINS 7 S Q3 Q2 Q1 R3 R2 R1
#$ INTERFACE rs 3 r'i' s'i' q'o'
#$ INSTANCE I1 rs 3 R
www.eeworm.com/read/251270/12355084
blo 3rs.blo
#$ TOOL ispLEVER 5.0.01.73.31.05_Starter
#$ DATE Mon Aug 14 19:03:34 2006
#$ TITLE 3rs.bls
#$ MODULE 3rs
#$ PINS 7 S Q3 Q2 Q1 R3 R2 R1
#$ INTERFACE rs 3 r'i' s'i' q'o'
#$ INSTANCE I1 rs 3 R
www.eeworm.com/read/251270/12355132
bl0 3rs.bl0
#$ TOOL ispLEVER 5.0.01.73.31.05_Starter
#$ DATE Mon Aug 14 19:03:34 2006
#$ TITLE 3rs.bls
#$ MODULE 3rs
#$ PINS 7 S Q3 Q2 Q1 R3 R2 R1
#$ INTERFACE rs 3 r'i' s'i' q'o'
#$ INSTANCE I1 rs 3 R
www.eeworm.com/read/251270/12355148
abt protect.abt
MODULE protect
" TOOL: ispLEVER
" DATE: Thu Sep 14 11:01:44 2006
" TITLE: protect.bls
" MODULE: protect
" DESIGN: protect
" FILENAME: protect.abt
" PROJECT: protect
" V
www.eeworm.com/read/265611/11260142
log automake.log
ispLEVER Auto-Make Log File
---------------------------
Starting: 'C:\ispTOOLS\ispcpld\bin\checkini.exe -err=automake.err "C:\ispTOOLS\ispcpld\config\plsi.ini"'
Done: completed successfully.
www.eeworm.com/read/238365/13891234
v fifo_tmpl.v
/* Verilog module instantiation template generated by SCUBA ispLever_v51_SP2_Build (10) */
/* Module Version: 2.0 */
/* Wed Apr 19 15:02:43 2006 */
/* parameterized module instance */
fifo __ (.Data(
www.eeworm.com/read/424814/10410221
udo uart_tb_tf.udo
-- ispLEVER Verilog Timing Simulation Template: uart_tb_tf.udo.
-- You may edit this file to control your simulation.
-- You may specify your design unit.
-- You may specify your waveforms.
add wa