fifo_tmpl.v

来自「使用Verilog语言编写」· Verilog 代码 · 共 9 行

/* Verilog module instantiation template generated by SCUBA ispLever_v51_SP2_Build (10) */
/* Module Version: 2.0 */
/* Wed Apr 19 15:02:43 2006 */

/* parameterized module instance */
fifo __ (.Data( ), .WrClock( ), .RdClock( ), .WrEn( ), .RdEn( ), 
    .Reset( ), .RPReset( ), .Q( ), .Empty( ), .Full( ), .AlmostEmpty( ), 
    .AlmostFull( ));