addr_select.bl1

一个组合逻辑实例,完成地址选择,读写信号产生等时序

#$ TOOL ispLEVER 5.1.02.70.06.06.SP2006.02
#$ DATE Sun Dec 03 17:53:45 2006
#$ MODULE addr_select
#$ PINS 11 a_2_ s_7_ a_1_ a_0_ s_6_ s_5_ s_4_ s_3_ s_2_ s_1_ s_0_

.model addr_select
.inputs a_2_.BLIF a_1_.BLIF a_0_.BLIF
.outputs s_7_ s_6_ s_5_ s_4_ s_3_ s_2_ s_1_ s_0_
.names s_7_
 0
.names s_6_
 0
.names s_5_
 0
.names s_4_
 0
.names s_3_
 0
.names a_2_.BLIF a_1_.BLIF a_0_.BLIF s_2_
100 1
-1- 0
0-- 0
--1 0
.names a_2_.BLIF a_1_.BLIF a_0_.BLIF s_1_
010 1
-0- 0
1-- 0
--1 0
.names a_2_.BLIF a_1_.BLIF a_0_.BLIF s_0_
001 1
-1- 0
1-- 0
--0 0
.end