代码搜索：integer
找到约 10,000 项符合「integer」的源代码
代码结果 10,000
www.eeworm.com/read/382183/9043175
vhd clockrun.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clockrun is
port( clk: in std_logic;
settime: in std_l
www.eeworm.com/read/185295/9044257
pas myfun.pas
unit myFun;
{-----------------------------------}
{ Create by 李金浩 }
{ QQ:67260745 }
{ 2004-3-21 }
{ 我的目标--共建理想常用函数库 }
{ in
www.eeworm.com/read/185287/9044731
txt delphi常用函数库.txt
delphi 常用函数库1 - 人生路上
您的查询字词都已标明如下：txt 行数 delphi (点击查询词，可以跳到它在文中首次出现的位置)
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(百度和网页http://www.honesed.com/blog/article.asp?id=110的作者无关，不对其内
www.eeworm.com/read/382145/9045674
vhd bslect.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity bslect is
port ( clk10k:in std_logic;
color:in integer range 0 to 2;
www.eeworm.com/read/382145/9045677
vhd slect.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity rslect is
port ( clk10k:in std_logic;
key1:in std_logic;
key2:in
www.eeworm.com/read/382145/9045703
vhd rrselect.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity rrselect is
port ( clk10k:in std_logic;
color:in integer range 0 to 2;
www.eeworm.com/read/382145/9045775
vhd gslect.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity gslect is
port ( clk10k:in std_logic;
color:in integer range 0 to 2;
www.eeworm.com/read/382145/9045821
vhd rrselect.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity rrselect is
port ( clk10k:in std_logic;
color:in integer range 0 to 2;
www.eeworm.com/read/185276/9046089
bas module1.bas
Attribute VB_Name = "Module1"
Public fMainForm As frmMain
Public gintSmode As Integer 'for service
Public gintPmode As Integer 'for plane
Public gintAmode As Integer 'for airline
Public gintTmode
www.eeworm.com/read/382145/9046113
vhd gslect.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity gslect is
port ( clk10k:in std_logic;
color:in integer range 0 to 2;