📄 clockrun.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clockrun is
port( clk: in std_logic;
settime: in std_logic;
hourhset: in integer range 0 to 2;
hourlset: in integer range 0 to 9;
minhset: in integer range 0 to 5;
minlset: in integer range 0 to 9;
sechset: in integer range 0 to 5;
seclset: in integer range 0 to 9;
hourhdis: out integer range 0 to 2;
hourldis: out integer range 0 to 9;
minhdis: out integer range 0 to 5;
minldis: out integer range 0 to 9;
sechdis: out integer range 0 to 5;
secldis: out integer range 0 to 9);
end clockrun;
architecture runarchi of clockrun is
signal seclow,minlow,hourlow: integer range 0 to 9;
signal sechigh,minhigh: integer range 0 to 5;
signal hourhigh: integer range 0 to 2;
begin
secldis<=seclow;
sechdis<=sechigh;
minldis<=minlow;
minhdis<=minhigh;
hourldis<=hourlow;
hourhdis<=hourhigh;
normal_run:
process(clk,settime)
begin
if settime='1' then
seclow<=seclset;
sechigh<=sechset;
minlow<=minlset;
minhigh<=minhset;
hourlow<=hourlset;
hourhigh<=hourhset;
else
if clk='1' and clk'event then
if seclow=9 then
seclow<=0;
if sechigh=5 then
sechigh<=0;
if minlow=9 then
minlow<=0;
if minhigh=5 then
minhigh<=0;
if hourlow=9 then
hourlow<=0;
hourhigh<=hourhigh+1;
elsif hourlow=3 and hourhigh=2 then
hourhigh<=0;
hourlow<=0;
else hourlow<=hourlow+1;
end if;
else
minhigh<=minhigh+1;
end if;
else
minlow<=minlow+1;
end if;
else
sechigh<=sechigh+1;
end if;
else
seclow<=seclow+1;
end if;
end if;
end if;
end process;
end runarchi;
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