rrselect.vhd

pwm控制模块 使用过很多次

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity rrselect is
port ( clk10k:in std_logic;
       color:in integer range 0 to 2;
       key2:in std_logic;
       key3:in std_logic;      
       rpwm0_ctr:out integer range 16 to 64;
       rpwm1_ctr:out integer range 16 to 64;
       rpwm2_ctr:out integer range 16 to 64;
       rpwm3_ctr:out integer range 16 to 64;
       rpwm4_ctr:out integer range 16 to 64;
       rpwm5_ctr:out integer range 16 to 64;
       rpwm6_ctr:out integer range 16 to 64;
       rpwm7_ctr:out integer range 16 to 64;
       rpwm8_ctr:out integer range 16 to 64;
       rpwm9_ctr:out integer range 16 to 64;
       rpwm10_ctr:out integer range 16 to 64;
       rpwm11_ctr:out integer range 16 to 64;
       rpwm12_ctr:out integer range 16 to 64;
       rpwm13_ctr:out integer range 16 to 64;
       rpwm14_ctr:out integer range 16 to 64;
       rpwm15_ctr:out integer range 16 to 64
       );
end rrselect;

architecture rsle of rrselect is
signal branch:integer range 0 to 15;
signal ctr:integer range 16 to 64;
signal ctr0:integer range 16 to 64;
signal ctr1:integer range 16 to 64;
signal ctr2:integer range 16 to 64;
signal ctr3:integer range 16 to 64;
signal ctr4:integer range 16 to 64;
signal ctr5:integer range 16 to 64;
signal ctr6:integer range 16 to 64;
signal ctr7:integer range 16 to 64;
signal ctr8:integer range 16 to 64;
signal ctr9:integer range 16 to 64;
signal ctr10:integer range 16 to 64;
signal ctr11:integer range 16 to 64;
signal ctr12:integer range 16 to 64;
signal ctr13:integer range 16 to 64;
signal ctr14:integer range 16 to 64;
signal ctr15:integer range 16 to 64;
begin

process(key2,color)
begin
if color=0 then
if key2'event and key2='1' then
   if branch=15 then
      branch<=0;
   else branch<=branch+1;
   end if;
end if;
else null;
end if;
end process;


process(key3,color)
begin
if color=0 then
if key3'event and key3='1' then
   if branch=0 then
      if ctr0=64 then
         ctr0<=16;
      else ctr0<=ctr0+4;
      end if;
   elsif branch=1 then
      if ctr1=64 then
         ctr1<=16;
      else ctr1<=ctr1+4;
      end if;
   elsif branch=2 then
      if ctr2=64 then
         ctr2<=16;
      else ctr2<=ctr2+4;
      end if;
   elsif branch=3 then
      if ctr3=64 then
         ctr3<=16;
      else ctr3<=ctr3+4;
      end if;
   elsif branch=4 then
      if ctr4=64 then
         ctr4<=16;
      else ctr4<=ctr4+4;
      end if;
   elsif branch=5 then
      if ctr5=64 then
         ctr5<=16;
      else ctr5<=ctr5+4;
      end if;
   elsif branch=6 then
      if ctr6=64 then
         ctr6<=16;
      else ctr6<=ctr6+4;
      end if;
   elsif branch=7 then
      if ctr7=64 then
         ctr7<=16;
      else ctr7<=ctr7+4;
      end if;
    elsif branch=8 then
      if ctr8=64 then
         ctr8<=16;
      else ctr8<=ctr8+4;
      end if;
    elsif branch=9 then
      if ctr9=64 then
         ctr9<=16;
      else ctr9<=ctr9+4;
      end if;
    elsif branch=10 then
      if ctr10=64 then
         ctr10<=16;
      else ctr10<=ctr10+4;
      end if;
    elsif branch=11 then
      if ctr11=64 then
         ctr11<=16;
      else ctr11<=ctr11+4;
      end if;
    elsif branch=12 then
      if ctr12=64 then
         ctr12<=16;
      else ctr12<=ctr12+4;
      end if;
    elsif branch=13 then
      if ctr13=64 then
         ctr13<=16;
      else ctr13<=ctr13+4;
      end if;
    elsif branch=14 then
      if ctr14=64 then
         ctr14<=16;
      else ctr14<=ctr14+4;
      end if;
    elsif branch=15 then
      if ctr15=64 then
         ctr15<=16;
      else ctr15<=ctr15+4;
      end if;


    end if;
end if;
else null;
end if;
end process;



rpwm0_ctr<=ctr0;
rpwm1_ctr<=ctr1;
rpwm2_ctr<=ctr2;
rpwm3_ctr<=ctr3;
rpwm4_ctr<=ctr4;
rpwm5_ctr<=ctr5;
rpwm6_ctr<=ctr6;
rpwm7_ctr<=ctr7;
rpwm8_ctr<=ctr8;
rpwm9_ctr<=ctr9;
rpwm10_ctr<=ctr10;
rpwm11_ctr<=ctr11;
rpwm12_ctr<=ctr12;
rpwm13_ctr<=ctr13;
rpwm14_ctr<=ctr14;
rpwm15_ctr<=ctr15;

end rsle;